NB100LVEP91_16 datasheet(6/11 Pages) ONSEMI

Part #	NB100LVEP91

Description	2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator

Download	11 Pages

Scroll/Zoom	100%

Manufacturer	ONSEMI [ON Semiconductor]

Direct Link	http://www.onsemi.com

Logo

6 / 11 page

NB100LVEP91

www.onsemi.com

6

Table 7. AC CHARACTERISTICS (VCC = 2.375 V to 3.8 V; VEE = −2.375 V to −3.8 V; GND = 0 V)

Symbol

Characteristic

−40°C

25°C

85°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

VOUTPP Output Voltage Amplitude (Figure 4) (Note 1)

fin V 1.0 GHz

fin V 1.5 GHz

fin V 2.0 GHz

575

525

300

800

750

600

525

250

800

750

550

400

150

800

750

500

mV

tPLH

tPHL0

Propagation Delay

Differential

D to Q

Single-Ended

375

300

500

450

600

650

375

300

500

450

600

675

400

300

550

500

650

750

ps

tSKEW

Pulse Skew (Note 2)

Output-to-Output (Note 3)

Part-to-Part (Diff) (Note 3)

15

25

50

75

95

125

15

30

50

75

105

125

15

30

70

80

105

150

ps

tJITTER

RMS Random Clock Jitter (Note 4)

fin = 2.0 GHz

Peak-to-Peak Data Dependant Jitter (Note 5)

fin = 2.0 Gb/s

0.5

20

2.0

0.5

20

2.0

0.5

20

2.0

ps

VINPP

Input Voltage Swing (Differential Configuration)

(Note 6)

200

800

1200

200

800

1200

200

800

1200

mV

tr, tf

Output Rise/Fall Times @ 50 MHz

(20% − 80%) Q, Q

75

150

250

75

150

250

75

150

275

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to GND − 2.0 V. Input edge rates 150 ps (20% − 80%).

2. Pulse Skew = |tPLH − tPHL|

3. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.

4. RMS Jitter with 50% Duty Cycle Input Clock Signal.

5. Peak-to-Peak Jitter with input NRZ PRBS 231−1 at 2.0 Gb/s.

6. Input voltage swing is a single-ended measurement operating in differential mode. The device has a DC gain of ≈ 50.

Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.

Input Frequency (fin) at Ambient Temperature (Typical)

INPUT FREQUENCY (GHz)

0.5

1.0

1.5

2.0

2.5

250

350

450

550

650

750

850

9.0

8.0

10

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0

RMS JITTER

AMP

Similar Part No. - NB100LVEP91_16

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	NB100LVEP91DW	76Kb / 8P	2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator January, 2003 - Rev. 2
	NB100LVEP91DW	145Kb / 10P	2.5 V/3.3 V Any Level Positive Input to ??.5 V/??.3 V LVNECL Output Translator November, 2006 ??Rev. 13
	NB100LVEP91DWG	145Kb / 10P	2.5 V/3.3 V Any Level Positive Input to ??.5 V/??.3 V LVNECL Output Translator November, 2006 ??Rev. 13
	NB100LVEP91DWR2	76Kb / 8P	2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator January, 2003 - Rev. 2
	NB100LVEP91DWR2	145Kb / 10P	2.5 V/3.3 V Any Level Positive Input to ??.5 V/??.3 V LVNECL Output Translator November, 2006 ??Rev. 13

More results

Similar Description - NB100LVEP91_16

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	NB100LVEP91	145Kb / 10P	2.5 V/3.3 V Any Level Positive Input to ??.5 V/??.3 V LVNECL Output Translator November, 2006 ??Rev. 13
	MC100EP91	168Kb / 10P	2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator August, 2006 ??Rev. 1
	MC100LVEL91	146Kb / 6P	3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator July, 2016 ??Rev. 12
Texas Instruments	SN74AUP1T32	167Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT,3.3-V CMOS OUTPUT, 2-INPUT POSITIVE-OR GATE
ON Semiconductor	NB6L11	212Kb / 12P	2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator November, 2006 ??Rev. 6
Analog Devices	ADG3242	680Kb / 16P	2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch REV. A
	ADG3242	247Kb / 12P	2.5 V/3.3 V, 2-Bit, Common Control Level Translator Bus Switch REV. 0
	ADG3243	187Kb / 12P	2.5 V/3.3 V, 2-Bit, Individual Control Level Translator Bus Switch REV. 0
Texas Instruments	SN74AUP1T00	164Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT POSITIVE-NAND GATE
Texas Instruments	SN74AUP1T02	164Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT,SINGLE 2-INPUT POSITIVE-NOR GATE

More results

NB100LVEP91 Datasheet(PDF) 6 Page - ON Semiconductor

NB100LVEP91 Datasheet(HTML) 6 Page - ON Semiconductor

Similar Part No. - NB100LVEP91_16

Similar Description - NB100LVEP91_16

Html Pages

1 2 3 4 5 6 7 8 9 10 11

Datasheet Download

Link URL