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82P33741 Datasheet(PDF) 7 Page - Integrated Device Technology |
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82P33741 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 61 page  7 ©2016 Integrated Device Technology, Inc. Revision 6, July 21, 2016 82P33741 Datasheet FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram Control and Status Registers OutDiv OutDiv I2C Slave JTAG I2C Master Reference monitors Reference selection Frac-N input dividers SYS PLL DPLL2 APLL1 APLL2 OutDiv OutDiv OutDiv DPLL1 OUT3p/n OUT4p/n OUT5p/n OUT6p/n OUT7 System Clock LOS0 / XO_FREQ0 LOS1 / XO_FREQ1 LOS2 / XO_FREQ2 LOS3 ex_sync module IN3(P/N) IN4(P/N) IN5(P/N) IN1(P/N) IN2(P/N) IN6(P/N) IN7 IN8 IN9 IN10 IN11 IN12 FRSYNC_8K_1PPS MFRSYNC_2K_1PPS Crystal OutDiv OUT1 OutDiv OUT2 OutDiv OutDiv OUT10p/n OUT11p/n APLL3 (VCXO) OutDiv OutDiv OUT8 OUT9 DPLL3 |
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