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82P33810 Datasheet(PDF) 3 Page - Integrated Device Technology

Part # 82P33810
Description  Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

82P33810 Datasheet(HTML) 3 Page - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
82P33810 Short Form Datasheet
Revision 6, March 29, 2016
In Synchronous Equipment Timing Source (SETS) applications per ITU-T G.8264, DPLL1 or DPLL2 can be configured as an EEC/SEC to output
clocks for the T0 reference point and DPLL3 can be used to output clocks for the T4 reference point.
Clocks generated by DPLL1 or DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The
output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.
The device provides an AMI output for a CC signal bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The CC output can be con-
nected to either DPLL1 or DPLL3.
All 82P33810 control and status registers are accessed through an I2C slave, SPI or the UART microprocessor interface. For configuring the
DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
Control and
Status
Registers
OutDiv
OutDiv
I2C Slave,
SPI, UART
JTAG
I2C Master
Reference
monitors
Reference
selection
Frac-N input
dividers
SYS PLL
DPLL2 /
DCO2
APLL1
APLL2
OutDiv
OutDiv
OutDiv
DPLL1 /
DCO1
OUT3p/n
OUT4p/n
OUT5p/n
OUT6p/n
OUT7
System Clock
LOS0 / XO_FREQ0
LOS1 / XO_FREQ1
LOS2 / XO_FREQ2
LOS3
ex_sync module
Composite
Clocks
IN1(CC)
IN2(CC)
IN5(P/N)
IN6(P/N)
IN7(P/N)
IN3(P/N)
IN4(P/N)
IN8(P/N)
IN9
IN10
IN11
IN12
IN13
IN14
FRSYNC_8K_1PPS
MFRSYNC_2K_1PPS
OutDiv
OUT1
OutDiv
OUT2
OutDiv
OutDiv
OUT10
OUT11
OUT9
Composite
Clock
DPLL3
ToD/ Time
Accumulator
ToD/ Time
Accumulator
OutDiv
OUT8


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