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©2016 Integrated Device Technology, Inc.

March 16, 2016

82P33813 Short Form Datasheet

50

SCLK/I2C_SCL

I

pull-down

CMOS

SCLK: Shift Clock

In Serial mode, a shift clock is input on this pin.

Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated

on the active edge of SCLK. The active edge is determined by the CLKE.

I2C_SCL: Serial Clock Line

In I2C mode, the serial clock is input on this pin.

51

SDO/I2C_SDA/

UART_TX

I/O

pull-up

CMOS/

Open Drain

SDO: Serial Data Output

In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked

out of the device on the active edge of SCLK.

I2C_SDA: Serial Data Input/Output

In I2C mode, this pin is used as the input/output for the serial data.

UART_TX:

In UART mode, this pin is used as the transmit data (UART Transmit)

JTAG (per IEEE 1149.1)

14

TMS

I

pull-up

CMOS

TMS: JTAG Test Mode Select

The signal on this pin controls the JTAG test performance and is sampled on the rising edge

of TCK.

15

TRSTB

I

pull-up

CMOS

TRSTB: JTAG Test Reset (Active Low)

A low signal on this pin resets the JTAG test port.

This pin should be connected to ground when JTAG is not used.

16

TCK

I

pull-down

CMOS

TCK: JTAG Test Clock

The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge

of TCK and TDO is updated on the falling edge of TCK.

If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely

retain their state.

17

TDI

I

pull-up

CMOS

TDI: JTAG Test Data Input

The test data are input on this pin. They are clocked into the device on the rising edge of

TCK.

18

TDO

O

tri-state

CMOS

TDO: JTAG Test Data Output

The test data are output on this pin. They are clocked out of the device on the falling edge of

TCK.

TDO pin outputs a high impedance signal except during the process of data scanning.

Power & Ground

2, 3, 4, 5, 10 11, 12

VDDA

Power

-

VDDA: Analog Core Power - +3.3V DC nominal

20, 24, 69, 72

VDDAO

Power

VDDAO: Analog Output Power - +3.3V DC nominal

27, 29, 64, 66

VDDDO

Power

VDDDO: Digital Output Power - +3.3V DC nominal

40, 62

VDDD

Power

VDDD: Digital Core Power - +3.3V DC nominal

42, 53

VDDD_1_8

Power

VDDD_1_8: Digital Core Power - +1.8V DC nominal

19,23

VSSAO

Ground

VSSAO: Ground

73 (e_PAD)

VSS

Ground

-

VSS: Ground

Other

1, 54, 56, 65, 67, 68, 70,

71

IC

-

-

IC: Internal Connection

Internal Use. These pins must be left open for normal operation.

Table 1: Pin Description (Continued)

Pin No.

Name

I/O

Type

Description