Triple 128-Position Nonvolatile Digital

Variable Resistor/Switch

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9

The following bus protocol has been defined:

Data transfer can be initiated only when the bus is

not busy.

During data transfer, the data line must remain sta-

ble whenever the clock line is high. Changes in the

data line while the clock line is high are interpreted

as control signals.

Accordingly, the following bus conditions have been

defined:

Bus Not Busy: Both data and clock lines remain

high.

Start Data Transfer: A change in the state of the

data line from high to low while the clock is high

defines a start condition.

Stop Data Transfer: A change in the state of the

data line from low to high while the clock line is

high defines the stop condition.

Data Valid: The state of the data line represents

valid data when, after a start condition, the data line

is stable for the duration of the high period of the

clock signal. The data on the line can be changed

during the low period of the clock signal. There is

STOP

CONDITION

OR REPEATED

START

CONDITION

REPEATED IF MORE BYTES

ARE TRANSFERRED

ACK

START

CONDITION

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

MSB

SCL

SDA

R/W

DIRECTION

BIT

12

6

7

8

9

12

8

9

3–7

Figure 2. 2-Wire Data Transfer Protocol

SDA

SCL

REPEATED

START

STOP

START

Figure 3. 2-Wire AC Characteristics