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NB100LVEP222 Datasheet(PDF) 10 Page - ON Semiconductor |
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NB100LVEP222 Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 13 page NB100LVEP222 www.onsemi.com 10 APPLICATIONS INFORMATION Using the thermally enhanced package of the NB100LVEP222 The NB100LVEP222 uses a thermally enhanced 52−lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100LVEP222 high−speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100LVEP222. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100LVEP222 applications on multi−layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 7 providing an efficient heat removal path. Figure 7. Recommended Thermal Land Pattern All Units mm Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern 4.6 4.6 The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 8, “Recommended solder mask openings”, shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 8. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. Figure 8. Recommended Solder Mask Openings All Units mm Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern 4.6 4.6 0.2 1.0 1.0 0.2 Proper thermal management is critical for reliable system operation. This is especially true for high−fanout and high output drive capability products. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 9. Thermal Resistance * lfpm qJA 5C/W qJC 5C/W 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * Junction to ambient and Junction to board, four−conductor layer test board (2S2P) per JESD 51−8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100LVEP222 package is electrically shorted to the substrate of the integrated circuit and VEE. The thermal land should be electrically connected to VEE. |
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