NB100LVEP222

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3

Figure 2. QFN−52 Pinout (Top View)

VCC

VCC0

Qc0

MR

CLK_SEL

Qc2

Qc3

1

2

3

4

5

6

7

8

9

10

11

12

13

fsela

fselb

CLK0

CLK0

VBB

fselc

fseld

VEE

39

38

37

36

35

34

33

32

31

30

29

28

27

NC

VCC0

Qc3

Qc2

Qc1

Qc1

Qc0

Exposed Pad (EP)

NB100LVEP222

NC

VCC0

CLK1

CLK1

Table 1. PIN DESCRIPTION

FUNCTION

ECL Differential Input Clock

ECL Differential Input Clock

ECL Clock Select

ECL Master Reset

ECL Differential Outputs

ECL Differential Outputs

ECL Differential Outputs

ECL Differential Outputs

ECL

1 or 2 Select

Reference Voltage Output

Negative Supply

No Connect

PIN

CLK0*, CLK0**

CLK1*, CLK1**

CLK_Sel*

MR*

Qa0:1, Qa0:1

Qb0:2, Qb0:2

Qc0:3, Qc0:3

Qd0:5, Qd0:5

fseln*

NC

* Pins will default LOW when left open.

** Pins will default HIGH when left open.

*** The thermally conductive exposed pad on the bottom of the package is

Table 2. FUNCTION TABLE

Input

Function

Active

CLK0

÷1

MR

CLK_Sel

fseln

LH

Reset

CLK1

÷2