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P3P623S05BG.08TR Datasheet(PDF) 5 Page - ON Semiconductor |
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P3P623S05BG.08TR Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 8 page P3P623S05A/B, P3P623S09A/B http://onsemi.com 5 Table 8. SWITCHING CHARACTERISTICS Parameter Description Test Conditions Min Typ Max Units Input Frequency 20 50 MHz 1/t1 Output Frequency 30 pF load 20 50 MHz tD Duty Cycle (Notes 3, 4) = (t2/t1) * 100 Measured at VDD/2 40 50 60 % t3 Output Rise Time (Notes 3, 4) Measured between 0.8 V and 2.0 V 2.5 nS t4 Output Fall Time (Notes 3, 4) Measured between 2.0 V and 0.8 V 2.5 nS t5 Output−to−output skew (Notes 3, 4) All outputs equally loaded 250 pS t6 Delay, CLKIN Rising Edge to CLKOUT Rising Edge (Note 4) Measured at VDD/2 ±350 pS t7 Device−to−Device Skew (Note 4) Measured at VDD/2 on the CLKOUT pins of the device 700 pS tJ Cycle−to−cycle jitter (Notes 3, 4) Loaded outputs ±200 pS tLOCK PLL Lock Time (Note 4) Stable power supply, valid clock presented on CLKIN pin 1.0 mS 3. All parameters specified with 30 pF loaded outputs. 4. Parameter is guaranteed by design and characterization. Not tested in production. Switching Waveforms Figure 4. Duty Cycle Timing t2 t1 VDD/2 VDD/2 VDD/2 OUTPUT Figure 5. All Outputs Rise/Fall Time t3 OUTPUT t4 0.8V 2V 0.8V 2V Figure 6. Output−Output Skew t 5 OUTPUT OUTPUT VDD/2 VDD/2 |
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