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CS8411 Datasheet(PDF) 1 Page - Cirrus Logic |
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CS8411 Datasheet(HTML) 1 Page - Cirrus Logic |
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1 / 38 page  1 Copyright © Cirrus Logic, Inc. 1998 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CS8411 CS8412 Digital Audio Interface Receiver Features l Monolithic CMOS Receiver l Low-Jitter, On-Chip Clock Recovery 256x Fs Output Clock Provided l Supports: AES/EBU, IEC958, S/PDIF, & EIAJ CP-340 Professional and Consumer Formats l Extensive Error Reporting - Repeat Last Sample on Error Option l On-Chip RS422 Line Receiver l Configurable Buffer Memory (CS8411) Description The CS8411/12 are monolithic CMOS devices which re- ceive and decode audio data according to the AES/EBU, IEC958, S/PDIF, & EIAJ CP-340 interface standards. The CS8411/12 receive data from a transmission line, recover the clock and synchronization signals, and de- multiplex the audio and digital data. Differential or single ended inputs can be decoded. The CS8411 has a configurable internal buffer memory, read via a parallel port, which may be used to buffer channel status, auxiliary data, and/or user data. The CS8412 de-multiplexes the channel, user, and va- lidity data directly to serial output pins with dedicated output pins for the most important channel status bits. ORDERING INFORMATION See page 32. I SCK 12 FSYNC 11 SDATA 26 RXP 9 RXN 10 Audio Serial Port CS 24 RD/WR 23 A3-A0 4 D7-D0 8 Configurable Buffer Memory MCK 19 De-MUX RS422 Receiver CS8411 IEnable and Status ERF INT 25 14 Clock and Data Recovery AGND 21 FILT 20 VA+ 22 DGND 8 VD+ 7 SCK 12 FSYNC 11 SDATA 26 RXP 9 RXN 10 Audio Serial Port 14 28 Registers MCK 19 De-MUX RS422 Receiver CS8412 MUX 2 27 Clock and Data Recovery AGND 21 FILT 20 VA+ 22 DGND 8 VD+ 7 1 C U VERF M3 17 M2 18 M1 24 M0 23 MUX ERF 25 CBL 15 43 65 Ce/ Cd/ Cc/ Cb/ Ca/ C0/ F2 F1 F0 E2 E1 E0 16 SEL 13 CS12/ FCK 13 A4/FCK OCT ‘98 DS61F1 |
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