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CS8420 Datasheet(PDF) 8 Page - Cirrus Logic |
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CS8420 Datasheet(HTML) 8 Page - Cirrus Logic |
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8 / 80 page  CS8420 8 DS245PP2 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (T A = 25 °C; VA+ = VD+ = 5V ±5%, Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 20 pF) Notes: 9. If Fso or Fsi is lower than 46.875 kHz, then maximum CCLK frequency should be less than 128Fso and less than 128Fsi. This is dictated by the timing requirements necessary to access the Channel Status and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 8 kHz, so choosing CCLK of less than or equal to 1.024 MHz should be safe for all possible conditions 10. Data must be held for sufficient time to bridge the transition time of CCLK. 11. For fsck <1 MHz. Parameter Symbol Min Typ Max Units CCLK Clock Frequency (Note 9) fsck 0- 6.0 MHz CS High Time Between Transmissions tcsh 1.0 - - µs CS Falling to CCLK Edge tcss 20 - - ns CCLK Low Time tscl 66 - - ns CCLK High Time tsch 66 - - ns CDIN to CCLK Rising Setup Time tdsu 40 - - ns CCLK Rising to DATA Hold Time (Note 10) tdh 15 - - ns CCLK Falling to CDOUT Stable tpd -- 45 ns Rise Time of CDOUT tr1 -- 25 ns Fall Time of CDOUT tf1 -- 25 ns Rise Time of CCLK and CDIN (Note 11) tr2 - - 100 ns Fall Time of CCLK and CDIN (Note 11) tf2 - - 100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh Figure 3. SPI Mode Timing |
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