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CS61535A-IL1 Datasheet(PDF) 10 Page - Cirrus Logic

Part No. CS61535A-IL1
Description  T1/E1 LINE INTERFACE
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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THEORY OF OPERATION
Enhancements in CS61535A
The CS61535A provides higher performance and
more features than the CS61535 including:
• 50% lower power consumption,
• Internally matched transmitter output imped-
ance for improved signal quality,
• Optional AMI, B8ZS, HDB3 encoder/decoder
or external line coding support,
• Receiver AIS (unframed all ones) detection,
• ANSI T1.231-1993 compliant receiver Loss
of Signal (LOS) handling,
• Transmitter TTIP and TRING outputs are
forced low when TCLK is static,
• The Driver Performance Monitor operates
over a wider range of input signal levels.
• Elimination of the requirement that a refer-
ence clock be input on the ACLKI pin.
Existing designs using the CS61535 can be converted
to the higher performance, pin-compatible CS61535A
if the transmit transformer is replaced by a pin-com-
patible transformer with a new turns ratio and the 4.4
Ω resistor used in E1 75 Ω applications is shorted.
Introduction to Operating Modes
The CS61535A supports three operating modes
which are selected by the level of the MODE pin
as shown in Tables 1 and 2, Figure 7, and Figures
A1-A3 of the Applications section.
The CS61535A modes are Hardware Mode, Ex-
tended Hardware Mode, and Host Mode. In
Hardware and Extended Hardware Modes, discrete
pins are used to configure and monitor the device.
The Extended Hardware Mode provides a parallel
chip select input which latches the control inputs
allowing individual ICs to be configured using a
common set of control lines. In the Host Mode, an
external processor monitors and configures the de-
vice through a serial interface. There are thirteen
multi-function pins whose functionality is deter-
mined by the operating mode (see Table 2).
Transmitter
The transmitter takes data from a T1 (or E1) ter-
minal, attenuates jitter, and produces pulses of
appropriate shape. The transmit clock, TCLK,
and transmit data, TPOS & TNEG or TDATA, are
supplied synchronously. Data is sampled on the
falling edge of the input clock, TCLK.
Either T1 (DSX-1 or Network Interface) or E1
G.703 pulse shapes may be selected. Pulse shap-
ing and signal level are determined by "line
length select" inputs as shown in Table 3. The
MODE
HARDWARE
EXTENDED
HARDWARE
HOST
MODE-PIN
INPUT LEVEL
<0.2V
FLOAT, or
2.5V
>(RV+) - 0.2V
CONTROL
METHOD
INDIVIDUAL
CONTROL
LINES
INDIVIDUAL
CONTROL
LINES &
PARALLEL
CHIP
SELECT
SERIAL
µ-PROCESSOR
PORT
LINE CODE
ENCODER &
DECODER
NONE
AMI,
B8ZS,
HDB3
NONE
AIS DETECTION
NO
YES
NO
DRIVER
PERFORM-
ANCE MONITOR
YES
NO
YES
Table 1. Differences in Operating Modes
MODE
FUNCTION
PIN
HARDWARE
EXTENDED
HARDWARE
HOST
TRANSMITTER
3TPOS
TDATA
TPOS
4TNEG
TCODE
TNEG
RECEIVER/DPM
6
RNEG
BPV
RNEG
7
RPOS
RDATA
RPOS
11
DPM
AIS
DPM
17
MTIP
RCODE
MTIP
18
MRING
-
MRING
CONTROL
18
-
PCS
-
23
LEN0
LEN0
INT
24
LEN1
LEN1
SDI
25
LEN2
LEN2
SDO
26
RLOOP
RLOOP
CS
27
LLOOP
LLOOP
SCLK
28
TAOS
TAOS
CLKE
Table 2. Pin Definitions
CS61535A
10
DS40F2




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