PCS3P25811, PCS3P25812, PCS3P25814

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2

Figure 1. Block Diagram

Crystal

Oscillator

Frequency

Divider

Feedback

Divider

Input Decoder

Phase

Detector

Loop

Filter

VCO

Output

Divider

PLL

XOUT

VDD

S1

XIN /CLKIN

ModOUT

VSS

& Modulation Control

S0

FSEL

Table 1. PIN DESCRIPTION

Pin #

Pin Name

Type

Description

1

XIN / CLKIN

Input

Crystal connection or External Clock input.

2

VSS

Power

Ground to entire chip.

3

S1

Input

Digital 3 level logic input (1−M−0) used to select Center, Down and No spread options.

(Refer to Frequency Deviation Selection Table). Default = M.

4

S0

Input

Digital 3 level logic input (1−M−0) used to select Center, Down and No spread options.

(Refer to Frequency Deviation Selection Table). Default = M.

5

ModOUT

Output

Spread Spectrum Clock Output.

6

FSEL

Input

Frequency range select. Digital 3 level logic input (1−M−0) used to select Input Clock

frequency range (Refer to Input/Output Frequency Range Selection Table). Default = M.

7

VDD

Power

Power supply for the entire chip (2.8 V to 3.6 V).

8

XOUT

Output

Crystal connection. If using an external reference, this pin must be left unconnected.

Table 2. OUTPUT FREQUENCY RANGE SELECTION

FSEL (pin 6)

Part Number

Modulation Rate

PCS3P25811 (1x)

PCS3P25812 (2x)

PCS3P25814 (4x)

Input (MHz)

Output (MHz)

Input (MHz)

Output (MHz)

Input (MHz)

Output (MHz)

0

4 − 8

4 − 8

4 − 8

8 − 16

4 − 8

16 − 32

Input Frequency / 128

1

8 − 16

8 − 16

8 − 16

16 − 32

8 − 16

32 − 64

Input Frequency / 256

M

16 − 32

16 − 32

16 − 32

32 − 64

16 − 32

64 − 128

Input Frequency / 512