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CAT5269YI50 Datasheet(PDF) 4 Page - ON Semiconductor

Part # CAT5269YI50
Description  Dual Digital Potentiometer (POT)
Download  15 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT5269YI50 Datasheet(HTML) 4 Page - ON Semiconductor

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CAT5269
http://onsemi.com
4
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Temperature Under Bias
−55 to +125
C
Storage Temperature
−65 to +150
C
Voltage on Any Pin with Respect to VSS (Note 1)
−2.0 to +VCC + 2.0
V
VCC with Respect to Ground
−2.0 to +7.0
V
Package Power Dissipation Capability (TA = 25C)
1.0
W
Lead Soldering Temperature (10 s)
300
C
Wiper Current
6
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters
Ratings
Units
VCC
+2.5 to +6.0
V
Industrial Temperature
−40 to +85
C
Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Limits
Units
Min
Typ
Max
RPOT
Potentiometer Resistance (100 kW)
100
kW
RPOT
Potentiometer Resistance (50 kW)
50
kW
Potentiometer Resistance Tolerance
20
%
RPOT Matching
1
%
Power Rating
25C, each pot
50
mW
IW
Wiper Current
3
mA
RW
Wiper Resistance
IW = 3 mA @ VCC = 3 V
200
300
W
RW
Wiper Resistance
IW = 3 mA @ VCC = 5 V
100
150
W
VTERM
Voltage on any RH or RL Pin
VSS = 0 V
VSS
VCC
V
Resolution
0.4
%
Absolute Linearity (Note 4)
Rw(n)(actual)−R(n)(expected)
(Note 7)
1
LSB
(Note 6)
Relative Linearity (Note 5)
Rw(n+1)−[Rw(n)+LSB]
(Note 7)
0.2
LSB
(Note 6)
TCRPOT
Temperature Coefficient of RPOT
(Note 3)
300
ppm/C
TCRATIO
Ratiometric Temp. Coefficient
(Note 3)
20
ppm/C
CH/CL/CW
Potentiometer Capacitances
(Note 3)
10/10/25
pF
fc
Frequency Response
RPOT = 50 kW (Note 3)
0.4
MHz
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = RTOT / 255 or (RH − RL) / 255, single pot
7. n = 0, 1, 2, ..., 255


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