CAT5401

http://onsemi.com

7

Figure 2. Synchronous Data Timing

VALID IN

HI−Z

HI−Z

SCK

SI

SO

Figure 3. HOLD Timing

SCK

SO

HIGH IMPEDANCE

CS

HOLD

CS

10.This parameter is tested initially and after a design or process change that affects the parameter.

11. Dashed Line = mode (1, 1) − − − − − − −