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BH1730FVC-TR Datasheet(PDF) 4 Page - Rohm |
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BH1730FVC-TR Datasheet(HTML) 4 Page - Rohm |
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4 / 24 page  4/20 TSZ02201-0M3M0F616050-1-2 © 2012 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 BH1730FVC 8.Jun.2016 Rev.001 Electrical Characteristics (VCC = 3.0V, VDVI = 3.0V, Ta = 25°C, unless otherwise noted) Parameter Symbol Min Typ Max Unit Conditions Supply Current ICC1 － 150 200 µA EV = 100 lx (Note 1) CONTROL register(00h) = "03h" and the other registers are default. Power Down Current ICC2 － 0.85 1.5 µA No input Light All registers are default. Peak Wave Length of Type0 (Note 2) λp0 － 600 － nm Peak Wave Length of Type1 (Note 2) λp1 － 840 － nm ADC Count Value of Type0 D1k_0 1020 1200 1380 count EV = 1000 lx (Note 1) TIMING register(01h) = "DAh" GAIN register(07h) = "00h" ADC Count Value of Type1 D1k_1 153 180 207 count EV = 1000 lx (Note 1) TIMING register(01h) = "DAh" GAIN register(07h) = "00h" Dark (0 lx) Sensor Out of Type0 S0_0 0 0 2 count No input Light TIMING register(01h) = "DAh" GAIN register(07h) = "00h" Dark (0 lx) Sensor Out of Type1 S0_1 0 0 2 count No input Light TIMING register(01h) = "DAh" GAIN register(07h) = “00h” Gain x1 Resolution of Type0 (Note 2) rG1 － 0.83 － lx/count TIMING register(01h) = "DAh" (Note 1) Gain x2 Resolution of Type0 (Note 2) rG2 － 0.42 － lx/count TIMING register(01h) = "DAh" (Note 1) Gain x64 Resolution of Type0 (Note 2) rG64 － 0.014 － lx/count TIMING register(01h) = "DAh" (Note 1) Gain x128 Resolution of Type0 (Note 2) rG128 － 0.007 － lx/count TIMING register(01h) = "DAh" (Note 1) Measurement Time Tmt1 － 104.6 150 ms TIMING register(01h) = "DAh" Internal Clock Period Tint - 2.8 4.0 µs INT Output 'L' Voltage VINT 0 － 0.4 V IINT = 3 mA SCL, SDA Input 'H' Voltage 1 VIH1 0.7*VDVI － － V VDVI ≥ 1.8V SCL, SDA Input 'H' Voltage 2 VIH2 1.26 － － V 1.65V ≤ VDVI <1.8V SCL, SDA Input 'L' Voltage 1 VIL1 － － 0.3*VDVI V VDVI ≥ 1.8V SCL, SDA Input 'L' Voltage 2 VIL2 － － VDVI –1.26 V 1.65V ≤ VDVI < 1.8V SCL, SDA, INT Input 'H' Current IIH － － 10 µA SCL, SDA, INT Input 'L' Current IIL － － 10 µA I 2C SCL Clock Frequency fSCL － － 400 kHz I 2C Bus Free Time tBUF 1.3 － － µs I 2C Hold Time (Repeated) START Condition tHDSTA 0.6 － － µs I 2C Setup Time for a Repeated START Condition tSUSTA 0.6 － － µs I 2C Setup Time for STOP Condition tSUSTO 0.6 － － µs I 2C Data Hold Time tHDDAT 0 － 0.9 µs I 2C Data Setup Time tSUDAT 100 － － ns I 2C 'L' Period of the SCL Clock tLOW 1.3 － － µs I 2C 'H' Period of the SCL Clock tHIGH 0.6 － － µs I 2C SDA Output 'L' Voltage VOL 0 － 0.4 V IOL = 3 mA (Note 1) White LED is used as optical source. (Note 2) Not 100% Tested |
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