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BU2396KN Datasheet(PDF) 4 Page - Rohm |
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BU2396KN Datasheet(HTML) 4 Page - Rohm |
4 / 24 page BU2396KN 4/20 TSZ02201-0E3E0J500710-1-2 © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 04.Nov.2015 Rev.001 Electrical Characteristics (VDD=3.3V, Ta=25°C, Crystal =12.000000MHz, unless otherwise specified.) Parameter Symbol Limit Unit Conditions Min Typ Max Operating Circuit Current IDD - 23 35 mA At no load 【Output H Voltage】 TGCLK VOHT VDD-0.5 - - V When current load =-5.0mA VCLK VOHV VDD-0.5 - - V When current load =-5.0mA UCLK VOHU VDD-0.5 - - V When current load =-5.0mA 【Output L Voltage】 TGCLK VOLT - - 0.5 V When current load =5.0mA VCLK VOLV - - 0.5 V When current load =5.0mA UCLK VOLU - - 0.5 V When current load =5.0mA 【Pull-Up Resistance Value】 TGCLK_SEL1 TGCLK_SEL2 Pull-up R 125 250 375 K Ω Monitor pin = 0V (R=VDD/I) 【Pull-Down Resistance Value】 TGCLK_EN, TGCLK_PD VCLK_EN, VCLK_PD Pull-down R 25 50 75 K Ω Monitor pin = VDD (R=VDD/I) 【Output Frequency】 TGCLK SEL1:L SEL2:L TGCLK1 24.000000 MHz XTAL x (48/4)/6 TGCLK SEL1:L SEL2:H TGCLK2 30.000000 MHz XTAL x (60/4)/6 TGCLK SEL1:H TGCLK3 36.000000 MHz XTAL x (54/3)/6 VCLK VCLK 27.000000 MHz XTAL x (54/3)/8 UCLK UCLK 12.000000 MHz XTAL output 【Output waveform】 Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD Rise Time tR 2.0 nsec Period of transition time required for the output to reach 80% from 20% of VDD. Fall Time tF 2.0 nsec Period of transition time required for the output to reach 20% from 80% of VDD. 【Jitter】 Period-Jitter 1 σ P-J1 σ 50 psec (Note 1) Period-Jitter MIN-MAX P-J MIN-MAX 300 psec (Note 2) 【Output Lock-Time】 tLOCK 1 msec (Note 3) (Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN. If the input frequency is set to 12.000000MHz, the output frequency will be as listed above. (Note 1) Period- Jitter 1σ This parameter represents standard deviation ( =1σ) on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd. (Note 2) Period-Jitter MIN-MAX This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd. (Note 3) Output Lock-Time The Lock-Time represents elapsed time after power supply turns ON to reach a 3.0V voltage, after the system is switched from Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency, respectively. |
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