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S29GL01GT11FHByyx Datasheet(PDF) 4 Page - Cypress Semiconductor |
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S29GL01GT11FHByyx Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 105 page Document Number: 002-00247 Rev. *G Page 4 of 105 S29GL01GT, S29GL512T 1. Product Overview The GL-T family consists of 512-Mbit to 1-Gbit, 3.0 V core, Versatile I/O, non-volatile, flash memory devices. These devices have an 8-bit (byte) / 16-bit (word) wide data bus and use only byte / word boundary addresses. All read accesses provide 8/16 bits of data on each bus transfer cycle. All writes take 8/16 bits of data from each bus transfer cycle. Figure 1.1 Block Diagram : Note: ** Amax GL01GT = A25, Amax GL512T = A24. The GL-T family combines the best features of eXecute In Place (XIP) and Data Storage flash memories. This family has the fast random access of XIP flash along with the high density and fast program speed of Data Storage flash. Read access to any random location takes 100 ns to 120 ns depending on device density and I/O power supply voltage. Each random (initial) access reads an entire 32-byte aligned group of data called a Page. Other words within the same Page may be read by changing only the low order 4 bits of word address. Each access within the same Page takes 15 ns to 25 ns. This is called Page Mode read. Changing any of the higher word address bits will select a different Page and begin a new initial access. All read accesses are asynchronous. Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator Timer VCC Detector State Control Command Register VCC VSS V IO WE# WP#/ACC CE# OE# STB STB DQ15 - DQ0 Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix ** Amax – A0 (A-1) BYTE# |
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