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ISL6539IA Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6539IA Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 20 page  9 FN9144.4 June 6, 2005 Theory of Operation Operation The ISL6539 is a dual channel PWM controller intended for use in power supplies for graphic chipsets, SDRAM, DDR DRAM, or other power applications. The IC integrates two control circuits for two synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistive divider. The synchronous buck converters can operate from either an unregulated DC source with a voltage ranging from 5.0V to 15V, or from a regulated system rail of 3.3V or 5V. In either operational mode the controller is biased from the +5V source. The controllers operate in the current mode with input voltage feed-forward which simplifies feedback loop compensation and rejects input voltage variation. An integrated feedback loop compensation dramatically reduces the number of external components. The ISL6539 has a special means to rearrange its internal architecture into a complete DDR solution. When the DDR pin is set high, the second channel can provide the capability to track the output voltage of the first channel. The buffered reference voltage required by DDR memory chips is also provided. Initialization The ISL6539 initializes if at least one of the enable pins is set high. The Power-On Reset (POR) function continually monitors the bias supply voltage on the VCC pin, and initiates soft-start operation when EN1 or EN2 is high after the input supply voltage exceeds 4.45V. Should this voltage drop lower than 4.14V, the POR disables the chip. Soft-Start When soft-start is initiated, the voltage on the SOFT pin of the enabled channel starts to ramp up gradually with the internal 5µA current charging the soft-start capacitor. The output voltage follows the soft-start voltage. When the SOFT pin voltage reaches 0.9V, the output voltage comes into regulation. When the SOFT voltage reaches 1.5V, the power good (PGOOD) is enabled. The soft-start process is depicted in Figure 3. Even though the soft-start pin voltage continues to rise after reaching 1.5V, this voltage does not affect the output voltage. The soft-start time (the time from the moment when EN becomes high to the moment when PGOOD is reported) is determined by the following equation: The time it takes the output voltage to come into regulation can be obtained from the following equation. During soft-start, before the PGOOD pin is enabled, the undervoltage protection is prohibited. The overvoltage and overcurrent protection functions are enabled. If the output capacitor has residue voltage before start-up, both lower and upper MOSFETs are in off-state until the soft- start capacitor charges equal the VSEN pin voltage. This will ensure the output voltage starts from its existing voltage level. Output Voltage Program The output voltage of either channel is set by a resistive divider from the output to ground. The center point of the divider is connected to the VSEN pin as shown in Figure 4. The output voltage value is determined by the following equation. where 0.9V is the value of the internal reference. The VSEN pin voltage is also used by the controller for the power good function and to detect undervoltage and overvoltage conditions. Ch3 1.0V Ch2 2.0V Ch4 5.0V M1.00ms Ch1 5.0V 3 2 4 1 EN 0.9V 1.5V SOFT VOUT PGOOD FIGURE 3. START UP TSOFT 1.5 V Csoft × 5 µA ---------------------------------- = TRISE 0.6 TSOFT × = VO 0.9 V R1 R2 + ( ) • R2 ---------------------------------------------- = ISL6539 |
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