bq2023

SINGLEWIRE ADVANCED BATTERY MONITOR IC

FOR CELLULAR AND PDA APPLICATIONS

SLUS480B – MAY 2001

5

POST OFFICE BOX 655303

flash memory characteristics over recommended operating temperature and supply voltage

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Data retention

See Note 7

5

Years

Flash programming write-cycles

See Note 7

10,000

Cycles

t(BYTERPROG)

Byte programming time

See Note 7

200

µs

t(BLKERASE)

Block-erase time

60

µs +30 µs/byte, See Note 7

1,500

µs

ICC(PROG)

Flash-write supply current

VCC = 5, See Note 7

30

mA

ICC(ERASE)

Flash-erase supply current

VCC = 5, See Note 7

30

mA

NOTE 7: Assured by design. Not production tested.

SDQ communication timing specification over recommended operating temperature and pull-up

voltage (unless otherwise noted) (See Figures 2 through 6)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t(SLOT)

Bit cycle time (See Figure 1)

See Note 8

60

120

s

t(LOW1)

Write bit one time (See Figure 1)

See Note 8

1

15

µs

t(LOW0)

Write bit zero time (See Figure 2)

t(LOW0) must be less than t(SLOT), See Note 8

60

120

µs

t(REC)

Recovery time (See Figure 2)

See Note 8

1

µs

t(LOWR)

Read bit strobe time (See Figure 3)

See Note 8

1

15

µs

t(RDV)

Read data valid time (See Figure 3)

See Note 8

tLOWR

15

µs

t(REL)

Read data release time (See Figure

4)

See Note 8

30

µs

t(RSTL)

Reset time low (See Figure 5)

t(RSTL) + t(R) < 960 µs, See Note 8

480

µs

t(RSTH)

Reset time high (See Figure 5)

See Note 8

300

µs

t(PDH)

Presence pulse delay (See Figure 5)

See Note 8

15

60

µs

t(PDL)

Presence pulse delay (See Figure 5)

See Note 8

60

240

µs

NOTE 8: 5-k

Ω pullup on SDQ pin

timing requirements

t(LOW1)

t(SLOT)

VIHmin

VILmax

t(REC)

V(PU)

Figure 1. SDQ Write Bit-ONE Timing Diagram