bq26200

SLUS509A − DECEMBER 2001 − REVISED NOVEMBER 2004

9

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APPLICATION INFORMATION

sleep mode operation

The bq26200 begins low-power operation in response to the host issuing the sleep command. Before entering

the low-power state, the host processor writes the command to transfer the registers to flash. After the sleep

command is sent and the charge/discharge activity is less than the value indicated by the WOE bits shown in

Table 3, the chip clock is powered down and data acquisition functions cease except for self-discharge

detection. During device sleep the bq26200 periodically wakes briefly to maintain the self-discharge registers.

The bq26200 wakes on either a low-to-high or high-to-low transition on the HDQ pin.

Table 2. Operational States

MODE

ACTIVE REGISTERS

Normal

CCR, DCR, CTC, DTC, SDR

Sleep

SDR

Table 3. WOE Thresholds

WOE3–1 (HEX)

VWOE (mV)

0h

n/a

1h

3.516

2h

1.758

3h

1.172

4h

0.879

5h

0.703

6h

0.586

7h*

0.502

current sense offset calibration and compensation

compensation is required.

gas gauge control registers

The host maintains the charge and discharge and the self-discharge count registers (CCR, CTC, DCR, DTC,

and SCR). To facilitate this maintenance, the bq26200 CLR register resets the specific counter or register pair

to zero. The host system clears a register by writing the corresponding register bit to 1. When the bq26200

completes the reset, the corresponding bit in the CLR register is automatically reset to 0. Clearing the DTC or

CTC registers clears the MODE register bits STC/STD and sets the CTC/DTC count rates to the default value

of 1.138 counts per second.

device temperature measurement

description for more details.