Multirate Clock and Data Recovery

with Limiting Amplifier

4

_______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CML OUTPUT SPECIFICATIONS (SDO

±, SCLKO±)

Output Edge Speed

20% to 80%

110

ps

CML Output Differential Swing

Ω differential

600

800

1000

Clock-to-Q Delay

(Note 9)

-50

+50

ps

PLL ACQUISITION/LOCK SPECIFICATIONS

Tolerated Consecutive Identical

Digits

BER

2000

bits

Acquisition Time

Figure 4 (Note 10)

5.5

ms

LOL Assert Time

Figure 4

2.3

100.0

µs

Low-Frequency Cutoff for

DC-Offset Cancellation

CAZ = 0.1µF

4

kHz

CLOCK HOLDOVER SPECIFICATIONS

Reference Clock Frequency

Table 3

Maximum VCO Frequency Drift

(Note 11)

400

ppm

Note 5:

AC characteristics are guaranteed by design and characterization.

Note 6:

Jitter tolerance is guaranteed (BER

Note 7:

Note 8:

Note 9:

Relative to the falling edge of the SCLKO+ (Figure 3).

Note 10: Measured using a 0.82µF loop-filter capacitor initialized to +3.6V.

Note 11: Measured at OC-48 data rate under LOL condition with the CDR clock output set by the external reference clock.

(a) AC-COUPLED SINGLE-ENDED INPUT

(b) DC-COUPLED SINGLE-ENDED INPUT

5mV

5mV

800mV

800mV

Figure 1. Definition of Input Voltage Swing

1.3

2.10

THRESHOLD-

SETTING

ACCURACY

(PART-TO-PART

VARIATION OVER

PROCESS)

+188

+170

+152

-152

-170

-188

THRESHOLD-SETTING STABILITY

(OVERTEMPERATURE AND POWER SUPPLY)

0.3

1.1

Figure 2. Relationship Between Control Voltage and Threshold

Voltage

Timing Diagrams