Datasheet

Datasheet

7/24

TSZ02201-0A0A2D300040-1-2

23.Jan.2015 Rev.003

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TSZ22111･15･001

BU9799KV

MAX 200 segments (SEG50×COM4)

○

Command transfer method

Issue Slave Address (“01111100”) after generation of “START condition”.

1byte after Slave Address always becomes command input.

MSB (“command or data judge bit”) of command decide if next data is command or display data.

When set “command or data judge bit”=‘1’, next byte data is command.

When set “command or data judge bit”=‘0’, next byte data is display data.

Slave address A 1

S

Command A 1 Command A 1 Command A 0 Command A

… P

Display Data

When display data is transferred, inputting of command is not allowed

When one wants to input command again, please generate “START condition” once.

If “START condition” or “STOP condition” are inputted in the middle of command transmission, command will be

canceled.

If Slave address is inputted after “START condition”, execution of command is allowed.

Please input “Slave Address” in the first data transmission after “START condition”.

When Slave Address cannot be recognized in the first data transmission, Acknowledge does not return and next

transmission will be invalid. When data transmission is invalid status, if “START conditions” are transmitted again, it will

return to valid status.

Take care to observe MPU Interface characteristic such as Input rise time and Setup/Hold time when transferring

command and data (Refer to MPU Interface).

○

Write display and transfer method

This device has Display Data RAM (DDRAM) of 50×4=200bits.

The relationship between data input and display data, DDRAM data and address are as follows;

01111100

A 0

S

0000000

A a b c d e f g h A i j k l m n o p

A … P

Display Data

Slave address

Command

8 bit data will be stored in DDRAM. The address to be written is the address specified by ADSET command, and the

address is automatically incremented in every 4bit data.

Data can be continuously written in DDRAM by transmitting Data continuously.

(When RAM data is written successively after writing RAM data to 31h (SEG49), the address is returned to 00h (SEG0)

by the auto-increment function.

DDRAM address

00

01

02

03

04

05

06

07

・・・

2Fh

30h

31h

BIT

0

a

e

i

m

COM0

1

b

f

j

n

COM1

2

c

g

k

o

COM2

3

d

h

l

p

COM3

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7

SEG47 SEG48 SEG49

Data transfer to DDRAM happens every 4bit data.

So it will be finished to transfer with no need to wait ACK.