CY7C1352F
Document #: 38-05211 Rev. *C
Page 3 of 13
Pin Definitions
Name
TQFP
I/O
Description
A0, A1, A
37,36,32,
33,34,35,
44,45,46,
47,48,49,
50,80,81,
82,99,100
Input-
Synchronous
Address Inputs used to select one of the 256K address locations. Sampled
at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:B]
93,94
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK.
WE
88
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is
active LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
85
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter or load a
new address. When HIGH (and CEN is asserted LOW) the internal burst counter
is advanced. When LOW, a new address can be loaded into the device for an
access. After being deselected, ADV/LD should be driven LOW in order to load
a new address.
CLK
89
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is
qualified with CEN. CLK is only recognized if CEN is active LOW.
CE1
98
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
CE2
97
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device.
CE3
92
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
86
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Combined with the
synchronous logic block inside the device to control the direction of the I/O pins.
When LOW, the DQ pins are allowed to behave as outputs. When deasserted
HIGH, DQ pins are three-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
CEN
87
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is
recognized by the SRAM. When deasserted HIGH the Clock signal is masked.
Since deasserting CEN does not deselect the device, CEN can be used to extend
the previous cycle when required.
ZZ
64
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has
to be LOW or left floating. ZZ pin has an internal pull-down.
DQs
58,59,62,
63,68,69,
72,73,
8,9,12,13,
18,19,22,
23
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the address during the clock rise
of the read cycle. The direction of the pins is controlled by OE and the internal
control logic. When OE is asserted LOW, the pins can behave as outputs. When
HIGH, DQs and DQP[A:B] are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQP[A:B]
74,24
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQs. During write sequences, DQP[A:B] is controlled by BW[A:B] correspondingly.
MODE
31
Input
Strap pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence.
VDD
15,41,65,
91
Power Supply
Power supply inputs to the core of the device.
VDDQ
4,11,20,27,54,6
1,70, 77
I/O Power
Supply
Power supply for the I/O circuitry.
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