DS1558

9 of 18

Table 3. ALARM MASK BITS

AM4

AM3

AM2

AM1

ALARM RATE

1

1

1

1

Once per second

1

1

1

0

When seconds match

1

1

0

0

When minutes and seconds match

1

0

0

0

When hours, minutes, and seconds match

0

0

0

0

When date, hours, minutes, and seconds match

When the RTC register values match alarm register settings, AF is set to a 1. If AE is also set to a 1, the

cleared by a read or write to the flags register, but the flag does not change states until the end of the

occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,

but an alarm generated during power-up sets AF. Therefore, the AF bit can be read after system power-up

to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm timing

during the backup-battery mode and power-up states.

Figure 2. CLEARING IRQ WAVEFORMS ACTIVE

Figure 3. CLEARING IRQ WAVEFORMS