LE25S20XA

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4

Device Operation

The read, erase, program and other required functions of the device are executed through the command registers.

The serial I/O corrugate is shown in Figure 3 and the command list is shown in Table 2. At the falling CS edge the

device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8

bit units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device

to execute operation according to the command that is input.

The LE25S20XA supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is

automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level

of SCK is high.

Figure 3 I/O waveforms

Table 2 Command Settings

Command

1st bus cycle

2nd bus

cycle

3rd bus cycle

4th bus cycle

5th bus cycle

6th bus cycle

Nth bus cycle

Read

03h

A23-A16

A15-A8

A7-A0

RD *1

RD *1

RD *1

0Bh

A23-A16

A15-A8

A7-A0

X

RD *1

RD *1

Small sector erase

20h / D7h

A23-A16

A15-A8

A7-A0

Sector erase

D8h

A23-A16

A15-A8

A7-A0

Chip erase

60h / C7h

Page program

02h

A23-A16

A15-A8

A7-A0

PD *2

PD *2

PD *2

Write enable

06h

Write disable

04h

Power down

B9h

Status register read

05h

Status register write

01h

DATA

JEDEC ID read

9Fh

ID read

ABh

X

X

X

power down

B9h

Exit power down mode

ABh

Explanatory notes for Table 2

"X" signifies "don't care" (that is to say, any value may be input).

The "h" following each code indicates that the number given is in hexadecimal notation.

Addresses A23 to A18 for all commands are "Don't care".

*1: "RD" stands for read data. *2: "PD" stands for page program data.

CS

SCK

SO

SI

High Impedance

DATA

DATA

1st bus

2nd bus

8CLK

Mode0

Mode3

Nth bus

MSB

(Bit7)

LSB

(Bit0)