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N24C32UDTG Datasheet(PDF) 3 Page - ON Semiconductor |
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N24C32UDTG Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 10 page N24C32 www.onsemi.com 3 Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICCR Read Current Read, fSCL = 1 MHz 0.4 mA ICCW Write Current Write 0.6 mA ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C 1 mA TA = −40°C to +125°C 2 IL I/O Pin Leakage Pin at GND or VCC 2 mA VIL1 Input Low Voltage 2.2 V ≤ VCC ≤ 5.5 V −0.5 0.3 VCC V VIL2 Input Low Voltage 1.6 V ≤ VCC < 2.2 V −0.5 0.2 VCC V VIH1 Input High Voltage 2.2 V ≤ VCC ≤ 5.5 V 0.7 VCC VCC + 0.5 V VIH2 Input High Voltage 1.6 V ≤ VCC < 2.2 V 0.8 VCC VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.2 V, IOL = 6.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.2 V, IOL = 2.0 mA 0.2 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Conditions Max Units CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF IWP, IA (Note 5) WP Input Current, Address Input Current (A0, A1, A2) VIN < VIH, VCC = 5.5 V 50 mA VIN < VIH, VCC = 3.3 V 35 VIN < VIH, VCC = 1.8 V 25 VIN > VIH 2 *VCC(min) = 1.6 V for Read operations, TA = −20°C to +85°C 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. |
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