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EP7212-CB-A Datasheet(PDF) 2 Page - Cirrus Logic |
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EP7212-CB-A Datasheet(HTML) 2 Page - Cirrus Logic |
2 / 136 page EP7212 Low-Power System-on-Chip with LCD Controller and Digital Audio Interface 2 DS474PP1 OVERVIEW (cont.) The EP7212 also includes a 32-bit Y2K-compliant realtime clock and comparator. Power Management The EP7212 is designed for ultra-low-power opera- tion. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V–3.3 V. The device has three basic power states: Operating — This state is the full performance state. All the clocks and peripheral logic are enabled. Idle — This state is the same as the Operating State, except the CPU clock is halted while wait- ing for an event such as a key press. Standby — This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor. Memory Interfaces There are two main external memory interfaces. The first one is the ROM / SRAM / FLASH-style inter- face that has programmable wait-state timings and includes burst-mode capability, with eight chip selects decoding six 256-Mbyte sections of addressable space. For maximum flexibility, each bank can be specified to be 8, 16, or 32 bits wide. This allows the use of 8-bit-wide boot ROM options to minimize over- FEATURES (cont.) n Advanced audio decoder / decompression capability — Allows for support of multiple audio decompression algorithms — Supports MPEG 1, 2, & 2.5 layer 3 audio decoding, including ISO compliant MPEG 1 & 2 layer 3 support for all standard sample rates and bit rates — Supports bit streams with adaptive bit rates — DAI (Digital Audio Interface) providing glueless interface to low-power DACs, ADCs, and Codecs n LCD controller — Interfaces directly to a single-scan panel monochrome LCD — Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments — Video frame buffer size programmable up to 128 kbytes — Bits per pixel of 1, 2, or 4 bits n DRAM controller — Supports both 16- and 32-bit-wide DRAMs — EDO support (Fast Page Mode support for 13 MHz and 18 MHz operation only) n Memory controller — Decodes up to 6 separate memory segments of up to 256 Mbytes each — Each segment can be configured as 8, 16, or 32 bits wide and supports page-mode access — Programmable access time for conventional ROM / SRAM / FLASH memory — Supports Removable FLASH card interface — Enables connection to removable FLASH card for addition of expansion FLASH memory modules n 38,400 bytes (0x9600) of on-chip SRAM for fast program execution and / or as a frame buffer n Synchronous serial interface — ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbps operation) n On-chip ROM; for manufacturing support n 27-bits of general-purpose I/O — Three 8-bit and one 3-bit GPIO port — Supports scanning keyboard matrix n Two UARTs (16550 type) — Supports bit rates up to 115.2 kbps — Contains two 16-byte FIFOs for TX and RX — UART1 supports modem control signals n SIR (up to 115.2 kbps) infrared encoder / decoder — IrDA (Infrared Data Association) SIR protocol encoder / decoder n DC-to-DC converter interface (PWM) — Provides two 96-kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a DC to DC converter n Two timer counters n 208-pin LQFP or new 256-ball PBGA packages n Evaluation kit available with BOM, schematics, sample code, and design database n Support for up to two ultra-low-power CL-PS6700 PC Card controllers n Dedicated LED flasher pin from RTC n Full JTAG boundary scan and Embedded ICE support n Commercial operating temperature range |
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