REVISION 2 08/17/16

7

2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER

8T74S208A-01 DATA SHEET

AC Electrical Characteristics

1

NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications

after thermal equilibrium has been reached under these conditions.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input

Frequency

IN, nIN

1GHz

400

kHz

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jitter Section, measured with

FSEL[1:0] = 00

Integration Range:

12kHz – 20MHz

96

120

fs

Propagation

NOTE 2: Measured from the differential input crosspoint to the differential output crosspoint.

IN, nIN to



Qx, nQx

FSEL[1:0] = 00

420

620

ps

FSEL[1:0] = 01

580

800

ps

FSEL[1:0] = 10

680

920

ps

FSEL[1:0] = 11

780

1050

ps

tsk(o)

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

45

ps

tsk(p)

Pulse Skew

FSEL[1:0] = 00

55

ps

tsk(pp)

NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-

spoint.

NOTE 6: Part-to-part skew specification does not guarantee divider synchronization among devices.

200

ps

odc

NOTE 7: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.

FSEL[1:0] = 00

50

%

FSEL[1:0] = 01

48

50

52

%

FSEL[1:0] = 10

48

50

52

%

FSEL[1:0] = 11

48

50

52

%

Output Enable and



Output Enable/ Disable State

from/ to Active/ Inactive

1µs

Output Rise/ Fall Time

20% to 80%

155

230

ps

10% to 90%

245

350

ps