N64S818HA

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11

READ Status Register Instruction (RDSR)

This instruction provides the ability to read the Status

register. The register may be read at any time by performing

the following timing sequence. Bits 0, 6 and 7 contain the

data for the functional operation and Bit 1 will read data type

‘1’ for the 64 Kb device.

CS

Instruction

SI

04

3

25

16

9

810

711

SCK

7

65

43

21

0

High−Z

Status Register Data Out

SO

00

0

00

1

0

12 13 14 15

1

Figure 16. READ Status Register Instruction (RDSR)

Figure 17. Status Register

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Hold Function

0 = Hold

1 = No Hold

Mode

0 0 = Word Mode

1 0 = Page Mode

0 1 = Burst Mode

1 1 = Reserved

0

0

0

0

1 = 64 Kb

Power−Up State

The serial SRAM enters a know state at power−up time. The device is in low−power standby state with CS = 1. A low level

on CS is required to enter an active state.