NCP1651DR2 datasheet(2/8 Pages) ONSEMI

Part #	NCP1651DR2

Description	Single Stage Power Factor Controller

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Manufacturer	ONSEMI [ON Semiconductor]

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Figure 2. Detailed Block Diagram

−

+

CNTRL

(3)

OUT

(1)

GND

(2)

−

+

LOGIC

BLOCK

DRIVER

Pre−

regulator

VCC

(5)

IN

(4)

ON/OFF

UVLO

OUT

V5

R1

R2

R3

R4

COMP

Bandgap

Reference

VCC

PIN FUNCTION DESCRIPTIONS

Pin #

Symbol

Pin Description

1

OUT

This signal drives the gate of a P−channel MOSFET. It is controlled by the voltage level on IN or the logic state

of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of VCC in

less than 1.0

msec provided that gate and stray capacitance is less than 12 nF.

2

GND

Circuit Ground

3

CNTRL

This logic signal is used to control the state of OUT and turn−on/off the P−channel MOSFET. A logic High

results in the OUT signal being driven to within 1.0 V of VCC which disconnects the FET. If this pin is not used,

the input should be connected to ground.

4

IN

This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold

(VTH), the OUT pin will be driven to within 1.0 V of VCC, thus disconnecting the FET. The nominal threshold

level is 6.85 V and this threshold level can be increased with the addition of an external resistor between IN

and VCC.

5

VCC

Positive Voltage supply. If VCC falls below 2.8 V (nom), the OUT pin will be driven to within 1.0 V of VCC, thus

disconnecting the P−channel FET.

TRUTH TABLE

IN

CNTRL

OUT

<Vth

L

GND

<Vth

H

VCC

>Vth

L

VCC

>Vth

H

VCC

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