Detailed Description

The DS1110L 10-tap delay line is a 3V version of

the DS1110. It has 10 equally spaced taps providing

delays from 10ns to 500ns. The device is offered in a

standard 14-pin TSSOP. The DS1110L series delay lines

provide a nominal accuracy of ±5% or ±2ns, whichever is

greater, at 3.3V and +25°C. The DS1110L is character-

ized to operate from 2.7V to 3.6V. The DS1110L repro-

duces the input-logic state at the tap 10 output after a

fixed delay as specified by the dash-number suffix of the

ing- and trailing-edge delays with equal precision. Each

tap is capable of driving up to 10 74LS-type loads. Dallas

Semiconductor can customize standard products to meet

specific needs. Figure 1 is the DS1110_L logic diagram

and Figure 2 shows the timing diagram for the silicon

delay line.

3V 10-Tap Silicon Delay Line

_____________________________________________________________________

5

10%

10%

IN

TAP1

TAP2

TAP9

TAP10

10%

10%

Figure 1. Logic Diagram

PART

TOTAL DELAY (ns)

DELAY/TAP (ns)

DS1110LE-100

100

10

DS1110LE-125

125

12.5

DS1110LE-150

150

15

DS1110LE-175

175

17.5

DS1110LE-200

200

20

DS1110LE-250

250

25

DS1110LE-300

300

30

DS1110LE-350

350

35

DS1110LE-400

400

40

DS1110LE-450

450

45

DS1110LE-500

500

50

IN

OUT

0.6V

2.4V

1.5V

1.5V

1.5V

1.5V

1.5V

0.6V

2.4V

PERIOD

Figure 2. Timing Diagram: Silicon Delay Line