TAS5001

SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

5

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functional description

serial audio port

The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin),

and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 32-kHz, 44.1-kHz,

48-kHz, 88.2-kHz, 96-kHz stereo). See the serial interface formats section for more information.

system clocks—master mode and slave mode

The TAS5001 allows multiple system clocking schemes. Master mode indicates that the TAS5001 provides

system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 256 Fs MCLK_OUT,

64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode

indicates that a system master other than the TAS5001 provides system clocks (LRCLK, SCLK, and MCLK_IN)

to the TAS5001 (M_S = 0). The TAS5001 operates with LRCLK and SCLK synchronized to MCLK. TAS5001

does not require any specific phase relationship between LRCLK and MCLK, but there must be synchronization.

In the slave mode MCLK_OUT is driven low. Table 1 shows all the possible master and slave modes.

oscillator/sampling frequency

The sampling frequency is determined by the crystal (master mode) or master clock in (slave mode) which

should be either 8.192 MHz (Fs = 32 kHz), 11.2896 MHz (Fs = 44.1 kHz), or 12.288 MHz (Fs = 48 kHz). Twice

the normal sampling frequency can be selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz

or Fs = 96 kHz. In the double-speed slave mode (DBSPD = 1, M_S = 0), the external clock input is either

22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz (Fs = 96 kHz). Note that 32-kHz sampling is supported in the

normal speed modes. Table 1 explains the proper clock selection.

Table 1. Oscillator, External Clock, and PLL Functions

DESCRIPTION

M_S

DBSPD

XTL_IN

(MHz)†

MCLK_IN

(MHz)‡

SCLK

(MHz)¶

LRCLK

(kHz)¶

MCLK_OUT

(MHz)#

Master, normal speed

1

0

8.192

—

2.048

32

8.192

Master, normal speed

1

0

11.2896

—

2.8224

44.1

11.2896

Master, normal speed

1

0

12.288

—

3.072

48

12.288

Master, double speed

1

1

—

22.5792§

5.6448

88.2

22.5792

Master, double speed

1

1

—

24.576§

6.144

96

24.576

Slave, normal speed

0

0

—

8.192§

2.048

32

Digital GND

Slave, normal speed

0

0

—

11.2896§

2.8224

44.1

Digital GND

Slave, normal speed

0

0

—

12.288§

3.072

48

Digital GND

Slave, double speed

0

1

—

22.5792§

5.6448

88.2

Digital GND

Slave, double speed

0

1

—

24.576§

6.144

96

Digital GND

† Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN.

‡ MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided.

§ External MCLK connected to MCLK_IN input

¶ SCLK and LRCLK are outputs when M_S=1, inputs when M_S=0.

# MCLK_OUT is driven low when M_S=0.

phase-locked loop (PLL)/clock generation

A low-jitter PLL is incorporated for internal use. Connections for the PLL external loop filter are provided as

PLL_FLT_RET and PLL_FLT_OUT. If the PLL loses lock, the PWM output status pins (VALID_L and VALID_R)

go low. Note that VALID_L and VALID_R can go low for other conditions as well. See the error status reporting

section for more information.