Flash Erasable,
Reprogrammable CMOS PAL Device
PALCE20V8
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03026 Rev. **
Revised March 26, 1997
20V8
Features
• Active pull-up on data input pins
• Low power version (20V8L)
— 55 mA max. commercial (15, 25 ns)
— 65 mA max. military/industrial
(15, 25 ns)
• Standard version has low power
— 90 mA max. commercial
(15, 25 ns)
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• QSOP package available
— 10, 15, and 25 ns com’l version
— 15, and 25 ns military/industrial versions
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE20V8 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-product (AND-OR) logic struc-
ture and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and a 24-lead
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 can be electrically erased and re-
programmed. The programmable macrocell enables the de-
vice to function as a superset to the familiar 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.
PAL is a registered trademark of Advanced Micro Devices, Inc.
Logic Block Diagram (PDIP/CDIP/QSOP)
20V8–1
88
88
8
8
8
8
10
9
8
7
6
5
432
1
13
15
16
17
18
19
20
21
22
23
PROGRAMMABLE
AND ARRAY
(64 x 40)
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
I9
I8
I7
I6
I5
I4
I3
I2
I1
CLK/I0
OE/I11
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I13
12
GND
11
I10
MUX
24
VCC
MUX
14
I12