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CS8401A-IP Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers |
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CS8401A-IP Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers |
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11 / 34 page  MSB last mode, or by restricting the number of SCK periods between samples to the sample word length. The 16-, 18-, and 20-bit LSB-last modes require at least 16, 18, or 20 SCK periods per sample respectively. As a master, 32 SCK pe- riods are output per sample. FSYNC must be derived from MCK via a DSP using the same clock or by external counters. If FSYNC moves (jitters) with respect to MCK by more than 4 MCK periods, the CS8401A may reset the channel status block and flags. Appen- dix C contains mo re information on the relationship of FSYNC and MCK. Buffer Memory In all buffer modes, the status register and con- trol registers are located at addresses 0-3 respectively, and the user data is buffered in lo- cations 4-7. The parallel port can access any location in the user data buffer at any time; how- ever, care must be taken not to modify a location when that location is being read internally. This internal reading is done through the second port of the buffer and is done in a cyclic manner. Reset in itializes th e internal pointer to 04H (Hex). Data is read from this location and stored in an 8-bit shift register which is shifted once per audio sample. (An audio sample is de- fined as a single channel, not a stereo pair.) The byte is transmitted LSB first, D0 being the first bit. After transmitting 8 samples, i.e. 8 user bits, the address pointer is incremented and the next byte of user data is loaded into the shift register. After transmitting all four bytes, 32 audio sam- 210 (bit) 000 001 010 100 110 FSF 00 01 10 11 00 01 10 11 MSTR 0 0 0 0 1 1 1 1 MSB First MSB Last LSB Last 16 LSB Last 18 LSB Last 20 FSYNC Input FSYNC Input FSYNC Input FSYNC Input FSYNC Output FSYNC Output FSYNC Output FSYNC Output Name LSB MSB LSB MSB LSB LSB LSB MSB LSB MSB LSB LSB MSB LSB MSB MSB LSB MSB LSB MSB MSB LSB MSB LSB MSB 16 Bits 18 Bits 20 Bits 18 Bits 16 Bits Left Sample Right Sample 20 Bits 16 Clocks 16 Clocks 16 Clocks 16 Clocks 32 Clocks 32 Clocks 32 Clocks 32 Clocks 10 (bit) SDF 24 bits, incl. Aux 24 bits, incl. Aux 24 bits, incl. Aux 24 bits, incl. Aux Figure 10. CS8401A Serial Port SDATA and FSYNC Timing CS8401A DS60F1 11 |
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