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EM68A16CBQC-18H Datasheet(PDF) 11 Page - Etron Technology, Inc. |
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EM68A16CBQC-18H Datasheet(HTML) 11 Page - Etron Technology, Inc. |
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11 / 62 page  EtronTech EM68A16CBQC Rev. 1.1 11 Jan. /2016 EMR(2) The extended mode register (2) controls refresh related features. The default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power-up for proper operation. The extended mode register(2) is written by asserting LOW on CS#, RAS#, CAS#, WE#, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. Table 7. Extended Mode Register EMR (2) Bitmap BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 1 0 0 *1 SRF 0 *1 DCC PASR *3 Extended Mode Register(2) A7 High Temperature Self-Refresh Rate Enable 0 Disable 1 Enable *2 BA1 BA0 MRS mode A3 DCC Enable *4 0 0 MR 0 Disable 0 1 EMR(1) 1 Enable 1 0 EMR(2) 1 1 EMR(3) A2 A1 A0 Partial Array Self Refresh for 4 Banks 0 0 0 Full array 0 0 1 Half Array (BA[1:0]=00&01) 0 1 0 Quarter Array (BA[1:0]=00) 0 1 1 Not defined 1 0 0 3/4 array (BA[1:0]=01,10&11) 1 0 1 Half array (BA[1:0]=10&11) 1 1 0 Quarter array (BA[1:0]=11) 1 1 1 Not defined NOTE 1: The rest bits in EMRS(2) are reserved for future use and all bits in EMRS(2) except A0-A2, A7, BA0 and BA1 must be programmed to 0 when setting the extended mode register(2) during initialization. NOTE 2: Due to the migration nature, user needs to ensure the DRAM part supports higher than 85℃ Tcase temperature self-refresh entry. If the high temperature self-refresh mode is supported then controller can set the EMRS2[A7] bit to enable the self-refresh rate in case of higher than 85℃ temperature self-refresh operation. NOTE 3: If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. NOTE 4: DCC (Duty Cycle Corrector) implemented, user may be given the controllability of DCC thru EMR (2) [A3] bit. |
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