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LMK61E2BBA-SIAT Datasheet(PDF) 1 Page - Texas Instruments |
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LMK61E2BBA-SIAT Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 55 page  ADD OUTN VDD OE GND OUTP SCL SDA 1 6 2 5 4 3 7 8 LMK61E2 Ultra-high performance oscillator PLL Output Divider Output Buffer Power Conditioning Interface I 2C/EEPROM Integrated Oscillator Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK61E2 SNAS674A – SEPTEMBER 2015 – REVISED APRIL 2016 LMK61E2 Ultra-Low Jitter Programmable Oscillator with Internal EEPROM 1 1 Features 1 • Ultra-Low Noise, High Performance – Jitter: 90 fs RMS Typical fOUT > 100 MHz – PSRR: –70 dBc, Robust Supply Noise Immunity • Flexible Output Format; User Selectable – LVPECL up to 1 GHz – LVDS up to 900 MHz – HCSL up to 400 MHz • Total frequency tolerance of ±50 ppm • System Level Features – Frequency Margining: Fine and Coarse – Internal EEPROM: User configurable Default Settings • Other Features – Device Control: I2C – 3.3-V Operating Voltage – Industrial Temperature Range (–40ºC to +85ºC) – 7-mm x 5-mm 8-Pin Package 2 Applications • High-Performance Replacement for Crystal-, SAW-, or Silicon-Based Oscillators • Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN • Test and Measurement • Medical Imaging • FPGA, Processor Attach 3 Description The LMK61E2 is an ultra-low jitter PLLatinumTM programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL or LVDS or HCSL. The device features self startup from on-chip EEPROM that is factory programmed to generate 156.25 MHz LVPECL output. The device registers and EEPROM settings are fully programmable in- system via I2C serial interface. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply. The device provides fine and coarse frequency margining options via I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMK61E2 8-pin QFM (SIA) 7.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Pinout and Simplified Block Diagram |
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