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TAS2557YZT Datasheet(PDF) 9 Page - Texas Instruments |
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TAS2557YZT Datasheet(HTML) 9 Page - Texas Instruments |
9 / 110 page 9 TAS2557 www.ti.com SLASEC2 – NOVEMBER 2016 Product Folder Links: TAS2557 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.6 I 2C Timing Requirements For I 2C interface signals over recommended operating conditions (unless otherwise noted). Note: All timing specifications are specified by design but not tested at final test. See Figure 1 PARAMETER TEST CONDITION Standard-Mode Fast-Mode UNITS MIN TYP MAX MIN TYP MAX fSCL SCL clock frequency 0 100 0 400 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 0.6 μs tLOW LOW period of the SCL clock 4.7 1.3 μs tHIGH HIGH period of the SCL clock 4 0.6 μs tSU;STA Setup time for a repeated START condition 4.7 0.6 μs tHD;DAT Data hold time: For I2C bus devices 0 3.45 0 0.9 μs tSU;DAT Data set-up time 250 100 ns tr SDA and SCL Rise Time 1000 20 + 0.1 × Cb 300 ns tf SDA and SCL Fall Time 300 20 + 0.1 × Cb 300 ns tSU;STO Set-up time for STOP condition 4 0.6 μs tBUF Bus free time between a STOP and START condition 4.7 1.3 μs Cb Capacitive load for each bus line 400 400 pF 7.7 SPI Timing Requirements For SPI interface signals over recommended operating conditions (unless otherwise noted). Note: All timing specifications are specified by design but not tested at final test. See Figure 2 PARAMETER TEST CONDITION IOVDD = 1.8 V IOVDD = 3.3 V UNITS MIN TYP MAX MIN TYP MAX tsck SCLK Period 40 30 ns tsckh SCLK Pulse width High 40 30 ns tsckl SCLK Pulse width Low 40 30 ns tlead Enable Lead Time 40 30 ns ttrail Enable Trail Time 40 30 ns td;seqxfr Sequential Transfer Delay 40 30 ns ta Slave DOUT access time 35 25 ns tdis Slave DOUT disable time 35 25 ns tsu DIN data setup time 8 8 ns th;DIN DIN data hold time 8 8 ns tv;DOUT DOUT data valid time 35 25 ns tr SCLK Rise Time 4 4 ns tf SCLK Fall Time 4 4 ns |
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