Datasheet

Datasheet

10/22

TSZ02201-0H3H0B600320-1-2

© 2012 ROHM Co., Ltd. All rights reserved.

3.AUG.2012 Rev.001

www.rohm.com

TSZ22111・15・001

BD65499MUV

(2) Logic output setting, STATE terminal output voltage

(3) Selection of the internal output signal of STATE terminal

* “&” means AND logic. “|” means OR logic.

(4) STATE terminal output voltage setting

* At the time of the falling edge of STATE terminal, it does latch the first changing signal from 1 to 0 in S_POWERGOOD, S_UVLOVCC2, S_TSD, S_(cl |

CLCANCEL) and other signals are hold as 1.

* At the time of a change VPSET[3:0] , it ignore the falling edge of the STATE terminal.

LSET

STATE terminal output

0

0 / 1.8V output

1

STATESEL

=3’d

Signal name

Function

0

ic & Power Good & uvlovcc2

& tsd& (cl | CLCANCEL)

ic, Power Good, UVLOVCC2, TSD, (cl | CLCANCEL) .If any one of

those signals is “0”(stand-by or abnormal condition) outputs Lo.

1

S_POWERGOOD &

S_UVLOVCC2 & S_TSD &

S_(cl | CLCANCEL)

S_ POWERGOOD, S_UVLOVCC2, S_TSD, S_(cl | CLCANCEL) If any

one of those signals is “0”(stand-by or abnormal condition) outputs Lo.

2

ic

Normal circuit condition signal (In stand-by mode, it outputs Lo signal)

3

S_POWERGOOD

Power Good signal for the latch (Original signal is Power Good)

4

S_UVLOVCC2

VCCUVLO2 signal for the latch (Original signal is uvlovcc2)

(In UVLO active mode, it outputs Lo signal)

5

-

-

6

S_TSD

Thermal shut down signal for the latch (Original signal is TSD)

(In Thermal shutdown condition, it outputs Lo signal)

7

S_(cl | CLCANCEL)

Current limit signal for the latch (Original signal is (cl | CLCANCEL)

Mode

PS

terminal

STATESET

S_POWER

GOOD &

S_UVLOVC

C2 &

S_TSD &

S_(cl |

CLCANCEL)

S_POWER

GOOD

S_UVLOVC

C2

S_TSD

S_(cl |

CLCANCEL)

STATESEL=3’

d1

STATESEL=3’

d3

STATESEL=3’

d4

STATESEL=3’

d6

STATESEL=3’

d7

Stand-by mode

L

0

L

(reset)

L

(reset)

L

(reset)

L

(reset)

L

(reset)

condition

H

0

L

(reset)

L

(reset)

L

(reset)

L

(reset)

L

(reset)

Circuit start up and the

voltage boost start

H

(after ic=1)

0

L

L

H

H

H

Condition that the

voltage boost complete

H

0

L→H

L→H

H

H

H

In the condition of

Boost voltage<（setting

70%）

H

0

H→L

(latch)

H→L

(latch)

H

(fix)

H

(fix)

H

(fix)

In the case of

H

0

H→L

(latch)

H

(fix)

H→L

(latch)

H

(fix)

H

(fix)

In the case of TSD

H

0

H→L

(latch)

H

(fix)

H

(fix)

H→L

(latch)

H

(fix)

In the case of

CLCANCEL=1’b0 and

Current limit condition

H

0

H→L

(latch)

H

(fix)

H

(fix)

H

(fix)

H→L

(latch)

In the condition of

STATESET=1’b1

H

1

H

(set)

H

(set)

H

(set)

H

(set)

H

(set)