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854S057B Datasheet(PDF) 11 Page - Integrated Device Technology

Part # 854S057B
Description  4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

854S057B Datasheet(HTML) 11 Page - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
Revision B, February 10, 2016
854S057B Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 854S057B.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 854S057B is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
Power (core)
MAX = V
DD_MAX * IDD_MAX = 2.625V * 50mA = 131.25mW
Power Dissipation for internal termination RT
Power (RT)MAX = 4 * (VPP_MAX)
2 / RT_MIN = (1.2V)2 / 80= 72mW
Total Power_MAX = 131.25mW + 72mW = 203.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.203W * 92.1°C/W = 103.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92.1°C/W
86.5°C/W
83.0°C/W


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