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8732-01 Datasheet(PDF) 10 Page - Integrated Device Technology

Part # 8732-01
Description  Low Voltage, Low Skew 3.3V LVPECL Clock Generator
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

8732-01 Datasheet(HTML) 10 Page - Integrated Device Technology

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8732-01 Data Sheet
©2016 Integrated Device Technology, Inc
Revision E January 22, 2016
10
C16
10uF
U1
ICS8732-01
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
DIV_SELA1
DIV_SELA0
VCC
VEE
CLK1
nCLK0
CLK0
CLK_SEL
VCCA
nc
DIV_SELB1
DIV_SELB0
VCC
VEE
FBDIV_SEL2
FBDIV_SEL1
FBDIV_SEL0
nFB_IN
FB_IN
VCC
VEE
nQFB0
QFB0
nQFB1
QFB1
VCCO
To Logic
Input
pins
R13
1K
C7
0.1uF
RD2
1K
R7
50
Logic Input Pin Examples
R14
1K
+
-
R7
10
DIV_SELA1
VCC
VCC
FBDIV_SEL2
C4
0.1uF
VCC=3.3V
R9
50
VCC
R12
50
+
-
R1
50
C5
0.1uF
VCCA
R6
50
(U1-1)
SP = Spare (i.e. not intstalled)
(U1-39)
Zo = 50
DIV_SELB1
R2
50
Zo = 50
VCC
Set Logic
Input to
'0'
Zo = 50
C3
0.1uF
Bypass capacitors located near the power pins
Zo = 50
Zo = 50
Zo = 50
To Logic
Input
pins
DIV_SELA0
FBDIV_SEL1
R11
50
RU2
SP
(U1-16)
C2
0.1uF
R8
50
DIV_SELB0
C8
0.1uF
Set Logic
Input to
'1'
FBDIV_SEL0
C6
0.1uF
RD1
SP
(U1-32)
C11
0.1uF
RU1
1K
(U1-26)
VCC
(U1-40)
VCC
R10
50
R3
50
(U1-46)
LVPECL
(U1-8)
C1
0.1uF
VCC
R5
50
R4
50
LAYOUT GUIDELINE
Figure 5 shows a schematic example of the 8732-01. In this
example, the CLK0/nCLK0 input is selected. The decoupling
capacitors should be physically located near the power pin. For
8732-01, the unused outputs can be left floating.
FIGURE 5. 8732-01 LVPECL BUFFER SCHEMATIC EXAMPLE


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