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83905AKLF Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 83905AKLF
Description  Low Skew, 1:6 Crystal-to-LVCMOS/ LVTTL Fanout Buffer
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

83905AKLF Datasheet(HTML) 8 Page - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
Revision D September 27, 2016
83905 Datasheet
Table 6E. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ
 f
MAX using a crystal input unless noted otherwise.
Terminated at 50
 to V
DDO/2.
NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
Table 6F. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ
 f
MAX using a crystal input unless noted otherwise.
Terminated at 50
 to V
DDO/2.
NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
Using External Crystal
10
40
MHz
Using External Clock
Source NOTE 1
DC
100
MHz
tsk(o)
Output Skew; NOTE 2, 3
80
ps
tjit
RMS Phase Jitter (Random)
25MHz, Integration Range:
100Hz – 1MHz
0.18
ps
tR / tF
Output Rise/Fall Time
20% to 80%
200
900
ps
odc
Output Duty Cycle
48
52
%
tEN
Output Enable
Time; NOTE 4
ENABLE1
4
cycles
ENABLE2
4
cycles
tDIS
Output Disable
Time; NOTE 4
ENABLE1
4
cycles
ENABLE2
4
cycles
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
Using External Crystal
10
40
MHz
Using External Clock
Source NOTE 1
DC
100
MHz
tsk(o)
Output Skew; NOTE 2, 3
80
ps
tjit
RMS Phase Jitter (Random)
25MHz, Integration Range:
100Hz – 1MHz
0.19
ps
tR / tF
Output Rise/Fall Time
20% to 80%
200
900
ps
odc
Output Duty Cycle
47
53
%
tEN
Output Enable
Time; NOTE 4
ENABLE1
4
cycles
ENABLE2
4
cycles
tDIS
Output Disable
Time; NOTE 4
ENABLE1
4
cycles
ENABLE2
4
cycles


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