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V6118 Datasheet(PDF) 3 Page - EM Microelectronic - MARIN SA |
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V6118 Datasheet(HTML) 3 Page - EM Microelectronic - MARIN SA |
3 / 15 page R V6118 Column Drivers Outputs FR Polarity COL Column Data Measured* Guaranteed S1 to S40 logic 1 logic 0 logic 1 ⏐ Sx* - VSS ⏐ S1 to S40 logic 0 logic 0 logic 1 ⏐ VLCD - Sx* ⏐ ¦ VLCD - Sx* ¦ = ¦ Sx* - VSS¦ ± 25 mV S1 to S40 logic 1 logic 0 logic 0 ⏐ VLCD - Sx* ⏐ S1 to S40 logic 0 logic 0 logic 0 ⏐ Sx* - VSS ⏐ ¦ VLCD - Sx* ¦ = ¦ Sx* - VSS¦ ± 25 mV Table 4a *Sx = the output number (ie. S1 to S40) Row Drivers Outputs FR Polarity COL Column Data Measured* Guaranteed S1 to Sn* logic 1 logic 1 logic 1 ⏐ VLCD - Sx ⏐ S1 to Sn* logic 0 logic 1 logic 1 ⏐ Sx - VSS ⏐ ¦ VLCD - Sx ¦ = ¦ Sx - VSS¦ ± 25 mV S1 to Sn* logic 1 logic 1 logic 0 ⏐ Sx - VSS ⏐ S1 to Sn* logic 0 logic 1 logic 0 ⏐ VLCD - Sx ⏐ ¦ VLCD - Sx ¦ = ¦ Sx - VSS¦ ± 25 mV Table 4b *n = the V6118 version no. (ie. 2, 4 or 8) Timing Characteristics VDD = 5V ± 10%, VLCD = 2 to 8V and TA = -40 to +85°C Parameter Symbol Test Conditions Min. Typ. Max. Units Clock high pulse width tCH 120 ns Clock low pulse width tCL 120 ns Clock and FR rise time tCR 200 ns Clock and FR fall time tCF 200 ns Data input setup time tDS 20 (note 1) ns Data input hold time tDH 30 (note 1) ns Data output propagation tPD CLOAD = 50pF 100 ns STR pulse width tSTR 100 ns CLK falling to STR rising tP 10 ns STR falling to CLK falling tD 200 ns FR frequency (vers. 2/4/8) FFR (note 2) 128/256/512 Hz Table 5a Note 1 : tDS + tDH minimum must be ≥ 100 ns. If tDS = 20 ns then tDH ≥ 80ns. Note 2 : V6118 n, FR = n times the desired LCD refresh rate where n is the V6118 version number. VDD = 2 to 6V, VLCD = 2 to 8V and TA = -40 to +85°C Parameter Symbol Test Conditions Min. Typ. Max. Units Clock high pulse width tCH 500 ns Clock low pulse width tCL 500 ns Clock and FR rise time tCR 200 ns Clock and RF fall time tCF 200 ns Data input setup time tDS 100 (note 1) ns Data input hold time tDH 150 (note 1) ns Data output propagation tPD CLOAD = 50pF 400 ns STR pulse width tSTR 500 ns CLK falling to STR rising tP 10 ns STR falling to CLK falling tD 1 µs FR frequency (Vers. 2/4/8) FFR (note 2) 128/256/512 Hz Table 5b Note 1 : tDS + tDH minimum must be ≥ 500 ns. If tDS = 100 ns then tDH ≥ 400ns. Note 2 : V6118 n, FR = n times the desired LCD refresh rate where n is the V6118 version number. Copyright © 2004, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com |
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