R

V6118

Column Drivers

Outputs

FR Polarity

COL

Column Data

Measured*

Guaranteed

S1 to S40

logic 1

logic 0

logic 1

⏐

S1 to S40

logic 0

logic 0

logic 1

⏐

S1 to S40

logic 1

logic 0

logic 0

⏐

S1 to S40

logic 0

logic 0

logic 0

⏐

Table 4a

*Sx = the output number (ie. S1 to S40)

Row Drivers

Outputs

FR Polarity

COL

Column Data

Measured*

Guaranteed

S1 to Sn*

logic 1

logic 1

logic 1

⏐

S1 to Sn*

logic 0

logic 1

logic 1

⏐

S1 to Sn*

logic 1

logic 1

logic 0

⏐

S1 to Sn*

logic 0

logic 1

logic 0

⏐

Table 4b

*n = the V6118 version no. (ie. 2, 4 or 8)

Timing Characteristics

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Units

Clock high pulse width

120

ns

Clock low pulse width

120

ns

Clock and FR rise time

200

ns

Clock and FR fall time

200

ns

Data input setup time

20 (note 1)

ns

Data input hold time

30 (note 1)

ns

Data output propagation

100

ns

STR pulse width

100

ns

CLK falling to STR rising

10

ns

STR falling to CLK falling

200

ns

FR frequency (vers. 2/4/8)

128/256/512

Hz

Table 5a

Note 1

Note 2

: V6118 n, FR = n times the desired LCD refresh rate where n is the V6118 version number.

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Units

Clock high pulse width

500

ns

Clock low pulse width

500

ns

Clock and FR rise time

200

ns

Clock and RF fall time

200

ns

Data input setup time

100 (note 1)

ns

Data input hold time

150 (note 1)

ns

Data output propagation

400

ns

STR pulse width

500

ns

CLK falling to STR rising

10

ns

STR falling to CLK falling

1

µs

FR frequency (Vers. 2/4/8)

128/256/512

Hz

Table 5b

Note 1

Note 2

: V6118 n, FR = n times the desired LCD refresh rate where n is the V6118 version number.

Copyright

© 2004, EM Microelectronic-Marin SA

3

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