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V61182 Datasheet(PDF) 10 Page - EM Microelectronic - MARIN SA |
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V61182 Datasheet(HTML) 10 Page - EM Microelectronic - MARIN SA |
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10 / 15 page  R V6118 Functional Description Supply Voltage VLCD, VDD, VSS The voltage between VDD and VSS is the supply voltage for the logic and the interface. The voltage between VLCD and VSS is the supply voltage for the LCD and is used for the generation of the internal LCD bias levels. The internal LCD bias levels have a maximum impedance of 25 k Ω for a VLCD voltage from 3 to 8V. Without external connections to the V1, V2, V3 bias level inputs, the V6118 can drive most medium sized LCD (pixel area up to 4'000 mm 2). For displays with a wide variation in pixel sizes, the configuration shown in Fig. 13 can give enhanced contrast by giving faster pixel switching times. On changing the row polarity (see Fig. 7, 8 and 9) the parallel capacitors lower the impedance of the bias level generation to the peak current, giving faster pixel charge times and thus a higher RMS "on" value. A higher RMS "on" value can give better contrast. IF for a given LCD size and operating voltage, the "off" pixels appear "on", or there is poor contrast, then an external bias level generation circuit can be used with the V6118. An external bias generation circuit can lower the bias level impedance and hence improve the LCD contrast (see Fig. 12). The optimum values of R, Rx and C, vary according to the LCD size used and VLCD. They are best determined through actual experimentation with the LCD. For LCD with very large average pixel area (eg. up to 10'000 mm 2), the bias level configuration shown in Fig. 14 should be used. When V6118s are cascaded, connect the V1, V2 and V3 bias inputs as shown in Fig. 10. The pixel load is averaged across all the cascaded drivers. This will give enhanced display contrast as the effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6118 are cascaded as shown in Fig. 10, then the maximum bias level impedance becomes 12.5 k Ω for a VLCD voltage from 3 to 8V. Table 8 shows the relationship between V1, V2 and V3 for the multiplex rates 2, 4 and 8. Note that VLCD > V1 > V2 > V3 for the V6118 2 and V6118 8, and for the V6118 4, VLCD > V1 > V2. Data Input /Output The data input pin, DI, is used to load serial data into the V6118. The serial data word length is 40 bits when COL is inactive, and 48 bits when it is active. Data is loaded in inverse numerical order, the data for bit 40 (bit 48 when COL is active) loaded first with the data for bit 1 last. The column data bits are loaded first and then the address bits (see Fig. 4 & 5). The data output pin, DO, is used in cascaded applications (see Fig. 10). DO transfers the data to the next cascaded chip. The data at DO is equal to the data at DI delayed by 40 clock periods, when COL is inactive and 48 clock periods when COL is active. In order to cascade V6118s, the DO of one chip must be connected to DI of the following chip (see Fig. 10). In cascaded applications the data for the last V6118 (the one that does not have DO connected) must be loaded first and the data for the first V6118 (its DI is connected to the processor) loaded last (see Fig. 10). The display RAM word length is 40 bits (see Fig. 6). Each LCD row has a corresponding display RAM address which provides the column data (on or off) when the row is selected (on). When downloading data to the V6118, any display selected RAM address can be chosen, there is no display RAM addressing sequence (see Fig.4 & 5). The same data can be written to more than one display RAM address. I fmore than one address bit is set, then more than one display RAM address is write enabled, and so the same data is written to more the one address. This feature can be useful to flash the LCD on and off under software control. If the address bits are all zero then no display RAM address is write enabled and no data is written to the display RAM on the falling edge of STR. Use address 0 to synchronize cascaded V6118s without updating the display RAM. CLK Input The CLK input is used to clock the DI serial data into the shift register and to clock the DO serial data out. Loading and shifting of the data occurs at the falling edge of this clock, outputting of the data at the rising edge (see Fig. 3). When cascading devices, all CLK lines should be tied together (see Fig. 10). STR Input The STR input is used to write to the display RAM, to blank the LCD, and synchronize cascaded V6118. The STR input writes the data loaded into the shift register, on the DI input, to the display selected RAM on the falling edge of the STR signal. The display RAM address is given by the address bits (see Fig. 4 & 5) The STR input when high blanks the LCD by disconnecting the internal voltage bias generation from the VSS potential. Segment outputs S1 to S40 (rows and columns) are pulled up to VLCD. The delay to driving the LCD with VLCD on S1 to S40, is dependent on the capacitive load of the LCD and is typically 1 µs. An LCD pixel responds to RMS voltage and takes approximately 100 ms to turn on or off. The delay from putting STR high to the LCD being blank is dependent on the LCD off time and is typically 100 ms. In applications which have a long STR pulse width (10 µs) the LCD is driven by VLCD on both the rows and columns during this time. As the time is short (1 µs), it will have zero measurable effect on the RMS "on" value (over 100 ms) of an LCD pixel and also zero measurable effect on the pixel DC component. Such STR pulses will not be visible to the human eye on an LCD. Note: if an external voltage bias generation circuit is used as shown in Fig. 12 to 14, the LCD blank function (STR high) will not blank the LCD. When STR is high, the LCD will be driven by the parallel combination of the external voltage bias generation circuit and part of the internal voltage bias generation circuit. The STR input, when high, synchronizes cascaded V6118s by forcing a new time frame to begin at the next falling edge of the FR input final (see Fig.6). A time frame begins with row 1 and so the LCD picture is rebuilt from row 1 each time cascaded V6118s are synchronized. When cascading devices, all STR lines must be tied together (see Fig. 10). FR Input The FR signal controls the segment output frequency generation (see Fig. 7, 8 and 9). To avoid having DC on the display, the FR signal must have a 50% duty cycle. The frequency of the FR signal must be n times the desired display refresh rate, where n is the V6118 version no. (2, 4 or 8). For example, if the desired refresh rate is 40 Hz, the FR signal frequency must be 320 Hz for the V6118 8. A selected row (on) is in phasewith the FR signal (see Fig. 7, 8 and 9). Copyright © 2004, EM Microelectronic-Marin SA 10 www.emmicroelectronic.com |
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