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V61184 Datasheet(PDF) 2 Page - EM Microelectronic - MARIN SA |
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V61184 Datasheet(HTML) 2 Page - EM Microelectronic - MARIN SA |
2 / 15 page R V6118 Absolute Maximum Ratings Parameter Symbol Conditions Supply voltage range VDD -0.3V to + 8V LCD supply voltage range VLCD -0.3V to + 9V Voltage at DI, DO, CLK, STR, FR, COL VLOGIC -0.3V to VDD+0.3V Voltage at V1 to V3, S1 to S40 VDISP -0.3V to VLCD + 0.3V Storage temperature range TSTO -65 to +150°C Power dissipation PMAX 100mW Electrostatic discharge max. to MIL-STD-883C method 3015.7 with ref. to VSS VSMAX 1000V Maximum soldering conditions TS 250°C x 10s Table 1 Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Symbol Min Typ Max Unit Operating Temperature TA -40 +85 °C Logic supply voltage VDD 2 5 6 V LCD supply voltage VLCD 2 5 8 V Table 2 Electrical Characteristics VDD = 5V ±10%, VLCD = 2 to 7V and TA = -40 to +85°C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units Dynamic supply current ILCD See note 1 100 150 µA Dynamic supply current IDD See note 1 at TA = 25°C 0.1 1 µA Dynamic supply current IDD See note 1 3 12 µA Dynamic supply current IDD See note 2 200 250 µA Standby supply current ISS See note 3 at TA = 25°C 0.1 1 µA Control Signals DI, CLK, STR, FR and COL Input leakage IIN 0 < VIN < VDD 1 100 nA Input capacitance CIN at TA = 25°C 8 pF Low level input voltage VIL 0 0.8 V High level input voltage for DI, STR, FR and COL VIH 2.0 VDD V High level input voltage for CLK VIH 3.0 VDD V Data Output DO High level output voltage VOH IH = 4 mA 2.4 V Low level output voltage VOL IL = 4 mA 0.4 V Driver Outputs S1 … S40 Driver impedance (note 4) ROUT IOUT = 10µA, VLCD = 7V 0.5 1.5 k Ω Driver impedance (note 4) ROUT IOUT = 10µA, VLCD = 3V 1.2 2.5 k Ω Driver impedance (note 4) ROUT IOUT = 10µA, VLCD = 2V 9 k Ω Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10µA, VLCD = 7V 16 20 k Ω Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10µA, VLCD = 3V 18 25 k Ω Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10µA, VLCD = 2V 30 k Ω DC output component ± VDC see Tables 4a & 4b, VLCD = 5V 30 50 mV Table 3 Note 1 : All outputs open, STR at VSS, FR = 400 Hz, all other inputs at VDD. Note 2 : All outputs open, STR at VSS, FR = 400 Hz, fCLK = 1 MHz, all other inputs at VDD. Note 3 : All outputs open, all other inputs at VDD. Note 4 : This is the impedance between of the voltage bias level pins (V1, V2 or V3) and the output pins S1 to S40 when a given voltage bias level is driving the outputs (S1 to S40) Note 5 : This is the impedance seen at the segment pin. Outputs measured one at a time. Copyright © 2004, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com |
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