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X9271TBI-2.7 Datasheet(PDF) 1 Page - Xicor Inc. |
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X9271TBI-2.7 Datasheet(HTML) 1 Page - Xicor Inc. |
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1 / 23 page  REV 1.1.7 2/6/03 Characteristics subject to change without notice. 1 of 23 www.xicor.com X9271 Single Digitally-Controlled (XDCPTM) Potentiometer FEATURES • 256 Resistor Taps • SPI Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100 Ω typical @ VCC = 5V • 16 Nonvolatile Data Registers • Nonvolatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power Up. • Standby Current < 3µA Max •VCC: 2.7V to 5.5V Operation • 50K Ω, 100KΩ versions of End to End Resistance • 100 yr. Data Retention • Endurance: 100,000 Data Changes per Bit per Register • 14-Lead TSSOP, 16-Lead CSP (Chip Scale Package) • Low Power CMOS DESCRIPTION The X9271 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Single Supply / Low Power / 256-tap / SPI bus APPLICATION NOTES AND DEVELOPMENT SYSTEM A V A I L A B L E AN99 • AN115 • AN124 •AN133 • AN134 • AN135 FUNCTIONAL DIAGRAM 50K Ω and 100KΩ RH RL RW POT VCC VSS SPI Bus Power On Recall Wiper Counter Register (WCR) Data Registers 16 Bytes Interface Bus Interface and Control Address Data Status Write Read Transfer Inc/Dec Control 256-taps |
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