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TDA1318 Datasheet(PDF) 5 Page - NXP Semiconductors |
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TDA1318 Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 24 page  April 1996 5 Philips Semiconductors Preliminary specification DCC read amplifier TDA1318 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION DCC data amplifiers For DCC operation the TDA1318 has eight channels for the main data and one channel for the auxiliary data. The eight main data channels have low-noise preamplifiers, pre-equalisation for frequencies from 1 kHz to 50 kHz (1st order high-pass filter, −3 dB point 75 kHz) and low-pass filtering for anti-aliasing (2nd order active, −3dB point 120 kHz). The auxiliary channel has a preamplifier with a flat frequency response. A continuous output (OUTX) is available for this channel. All inputs are differential and must be AC-coupled to the MRHs. The inputs are internally biased by V14. Automatic gain control The DCC part is equipped with an AGC circuit which diminishes the gain of the DCC preamplifiers when the level at output RDMUX exceeds a preset value. In this way, an optimum voltage swing at the RDMUX output is obtained. The response time of the AGC can be set by an external capacitor at pin 43. There is a fixed relation between the source and sink current at this pin. This results in a fixed relationship between decay and recovery time of the gain. The AGC can be switched off by connecting pin 43 to VSS. In this condition the preamplifier gains are maximum, as specified in Chapter “Characteristics”. Multiplexer A multiplexing circuit switches the nine digital channels sequentially to the output. The AUX data is switched to the output buffer during two clock periods, the eight main data channels are all sampled for one clock period. The effective sample frequency is one tenth of the clock frequency at RDCLK. Multiplexer timing is illustrated in Fig.4. |
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Similar Description - TDA1318 |
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