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MC74ACT253DG Datasheet(PDF) 2 Page - ON Semiconductor |
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MC74ACT253DG Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 9 page MC74AC253, MC74ACT253 www.onsemi.com 2 TRUTH TABLE Select Inputs Data Inputs Output Enable Outputs S0 S1 I0 I1 I2 I3 OE Z X X X X X X H Z L L L X X X L L L L H X X X L H H L X L X X L L H L X H X X L H L H X X L X L L L H X X H X L H H H X X X L L L H H X X X H L H Address inputs S0 and S1 are common to both sections. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance FUNCTIONAL DESCRIPTION The MC74AC253/74ACT253 contains two identical 4−input multiplexers with 3−state outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The 4−input multiplexers have individual Output Enable (OEa, OEb) inputs which, when HIGH, force the outputs to a high impedance (High Z) state. This device is the logic implementation of a 2−pole, 4−position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown: Za = OEa•(I0a•S1•S0+I1a•S1•S0+ I2a•S1•S0+I3a•S1•S0) Zb = OEb•(I0b•S1•S0+I1b•S1•S0+ I2b•S1•S0+I3b•S1•S0) If the outputs of 3−state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3−state devices whose outputs are tied together are designed so that there is no overlap. OEb I3b I2b I1b I0b S0 S1 I3a I2a Zb Za I1a I0a OEa NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram Figure 2. Logic Symbol S0 S1 OEa I0a I1a I2a I3a Za Zb I0b I1b I2b I3b OEb |
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