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AT45DB041B Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT45DB041B Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 33 page  9 AT45DB041B 1938F–DFLSH–10/02 WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. The WP pin is internally pulled high; therefore, connection of the WP pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the WP pin be driven high externally whenever possible. RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. The RESET pin is also internally pulled high; therefore, connection of the RESET pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the RESET pin be driven high exter- nally whenever possible. READY/BUSY: This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through a1 k W external pull-up resistor), will be pulled low during programming operations, com- pare operations, and during page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruc- tion. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. |
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