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SN65DSI84TPAPRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65DSI84TPAPRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 52 page  6 SN65DSI84-Q1 SLLSEW9 – DECEMBER 2016 www.ti.com Product Folder Links: SN65DSI84-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) The unit interval (UI) is one half of the period of the HS clock; at 500 MHz the minimum setup and hold time is 150 ps. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VCC VCC power supply 1.65 1.8 1.95 V VPSN Supply noise on any VCC pin ƒ(noise) > 1 MHz 0.05 V V(DSI) DSI input pin voltage –50 1350 mV ƒ(I2C) Local I2C input frequency 400 kHz ƒHS(CLK) DSI high-speed (HS) clock input frequency 40 500 MHz tsu DSI HS data to clock setup time 0.15 UI(1) th DSI HS data to clock hold time 0.15 UI(1) ZOD(LVDS) LVDS output differential impedance 90 132 Ω TC Case temperature 92.2 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.4 Thermal Information THERMAL METRIC(1) SN65DSI84-Q1 UNIT PAP (HTQFP) 64 PINS RθJA Junction-to-ambient thermal resistance 36.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.2 °C/W RθJB Junction-to-board thermal resistance 20.6 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 20.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W (1) All typical values are at VCC = 1.8V and TA = 25°C (2) SN65DSI84-Q1: SINGLE Channel DSI to DUAL Channel LVDS, 1400 x 900 (a) number of LVDS lanes = 2 × (3 data lanes + 1 CLK lane) (b) number of DSI lanes = 2 data lanes + 1 CLK lane (c) LVDS CLK OUT = 53.25 M (d) DSI CLK = 500 M (e) RGB888, LVDS18 bpp Maximum values are at VCC = 1.95 V and TA = 105°C 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIL Low-level control signal input voltage 0.3 × VCC V VIH High-level control signal input voltage 0.7 × VCC V VOH High-level output voltage IOH = –4 mA 1.25 V VOL Low-level output voltage IOL = 4 mA 0.4 V ILKG Input failsafe leakage current VCC = 0; VCC(PIN) = 1.8 V ±30 μA IIH High level input current Any input terminal ±30 μA IIL Low level input current Any input terminal ±30 μA IOZ High-impedance output current CMOS output terminals ±10 μA IOS Short-circuit output current Any output driving GND short ±50 mA ICC Device active current See (2) 106 164 mA IULPS Device standby current All data and clock lanes are in ultra-low power state (ULPS) 7.7 14 mA IRST Shutdown current EN = 0 0.04 130 µA REN EN control input resistor 200 kΩ |
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