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SN65DSI84 Datasheet(PDF) 9 Page - Texas Instruments |
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SN65DSI84 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 52 page  Low Power (LP) Mode Receiver LP-RX Input LOW LP-RX Input HIGH V IH(LP) GND V IL(LP) VIH(HS) High Speed (HS) Mode Receiver HS-RX Common Mode Range V CM(HS) V V ID VIL(HS) 1.3 V max CM(HS)min 9 SN65DSI84-Q1 www.ti.com SLLSEW9 – DECEMBER 2016 Product Folder Links: SN65DSI84-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT (2) For EMI reduction purpose, SN65DSI84-Q1 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or B_CLKP/N. EN, ULPS, RESET ten Enable time from EN or ULPS; see Figure 5 tc(o) = 12.9 ns 1 ms tdis Disable time to standby; see Figure 5 tc(o) = 12.9 ns 0.1 ms treset Reset Time 10 ms REFCLK FREFCLK REFCLK Freqeuncy. Supported frequencies: 25 MHz - 15 4MHz 25 154 MHz tr, tf REFCLK rise and fall time 0.1 1 ns tpj REFCLK Peak-to-Peak Phase Jitter 50 ps Duty REFCLK Duty Cycle 40% 50% 60% REFCLK or DSI CLK (DACP/N, DBCP/N) SSC_CLKIN SSC enabled Input CLK center spread depth(2) 0.5% 1% 2% Modulation Frequency Range 30 60 kHz 7 Parameter Measurement Information Figure 2. DSI Receiver Voltage Definitions |
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